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--- resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [03 Dec 2019 10:14] – Fix block diagram Stanca-Florina Pop
+++ resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [14 Jan 2021 05:38] (current) – use wiki interwiki links Robin Getz
@@ Line 372: / Line 372: @@
 ===== Building the HDL Project =====
-When building the project, you should always use the recommended version of the tools for the specific [[https://wiki.analog.com/resources/fpga/docs/releases | release]]. In this example, we'll use release 2018_r1, which has Vivado 2017.4.1 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.
+When building the project, you should always use the recommended version of the tools for the specific [[/resources/fpga/docs/releases | release]]. In this example, we'll use release 2018_r1, which has Vivado 2017.4.1 as the recommended version. If you're using different Vivado versions, it's possible that there are slight modifications on how the synthesis works, or different Xilinx IP changes, which affect the system functionality.
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