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| resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [15 Nov 2019 10:03] – Update block diagram Stanca-Florina Pop | resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [03 Dec 2019 10:14] – Fix block diagram Stanca-Florina Pop | ||
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| ==== Xilinx block diagram ==== | ==== Xilinx block diagram ==== | ||
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| The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface. | The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface. | ||
resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx.txt · Last modified: 14 Jan 2021 05:38 by Robin Getz