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resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [15 Nov 2019 10:03]
Stanca-Florina Pop Update block diagram
resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [03 Dec 2019 10:14]
Stanca-Florina Pop Fix block diagram
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 ==== Xilinx block diagram ==== ==== Xilinx block diagram ====
-{{resources:​eval:​user-guides:​ad-fmcdaq2-ebz:​daq2_xilinx_1.svg?​800|Xilinx HDL Block Diagram}}+{{resources:​eval:​user-guides:​ad-fmcdaq2-ebz:​daq2_xilinx_2.svg?​800|Xilinx HDL Block Diagram}}
  
  The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.  The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface.
resources/fpga/peripherals/jesd204/tutorial/hdl_xilinx.txt · Last modified: 14 Jan 2021 05:38 by Robin Getz