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resources:fpga:peripherals:jesd204:jesd204_troubleshooting [23 Jan 2020 10:15] – Laszlo Nagyresources:fpga:peripherals:jesd204:jesd204_troubleshooting [06 Feb 2020 16:52] – removed wraps Laszlo Nagy
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-===== Troubleshooting JESD204 Links ===== +===== Troubleshooting JESD20B Tx/DAC links =====
- +
-==== JESD20B Tx/DAC links ====+
  
 Running one of the below commands on a Linux based system will return the status of the JESD link. Running one of the below commands on a Linux based system will return the status of the JESD link.
Line 26: Line 24:
  
  
-<WRAP important> **Symptom:**\\ Missing JESD link layer peripheral, ***.axi-jesd*/status*: No such file or directory**+====Missing JESD link layer peripheral, *.axi-jesd*/status*: No such file or directory==== 
 +<WRAP center round box 100%>
  
-<WRAP alert> +**Cause:** Base address mismatch between HDL and device tree, adi,axi-jesd204-tx-1.0 or adi,axi-adxcvr-1.0 driver does not probes.
-**Cause:**\\  Base address mismatch between HDL and device tree, adi,axi-jesd204-tx-1.0 or adi,axi-adxcvr-1.0 driver does not probes. +
  
-<WRAP tip> +**Identify:** Check address allocation in the block design or system_bd.tcl against the corresponding device tree physical and link layer nodes.
-**Identify:**\\ Check address allocation in the block design or system_bd.tcl against the corresponding device tree physical and link layer nodes. +
  
-**Fix:**\\ Adjust addresses. For ZCU102 add 0x20000000 offset to the address used in HDL.  +**Fix:** Adjust addresses. For ZCU102 add 0x20000000 offset to the address used in HDL.
- +
-</WRAP> +
-</WRAP>+
 </WRAP> </WRAP>
  
 +----
  
-<WRAP important> **Symptom:**\\  +====Link is DISABLED, In Linux boot log following appears:  axi-adxcvr-tx: TX Error: 0==== 
-Link is DISABLED, In Linux boot log following appears:  **axi-adxcvr-tx: TX Error: 0**  +<WRAP center round box 100%> 
-<WRAP alert> +**Cause:** QPLL or CLL does not lock due missing reference clock.
-**Cause:**\\   +
- QPLL or CLL does not lock due missing reference clock.  +
-<WRAP tip> +
-**Identify:**\\ +
-Check reference clock location constraints. Check if ref clock reaches the in use quads.+
  
-**Fix:**\\ +**Identify:** Check reference clock location constraints. Check if ref clock reaches the in use quads.
-Adjust location constraints. +
-</WRAP> +
-</WRAP>+
  
-<WRAP alert> +**Fix:** Adjust location constraints.
-**Cause:**\\   +
- QPLL or CLL does not lock due incorrect synthesis parameters. +
  
-<WRAP tip> 
-**Identify:**\\ 
-Check channel and common util_adxcvr parameters against ones created with the transceiver wizard. 
- 
-**Fix:**\\ 
-Adjust synthesis parameters of the util_adxcvr component. 
-</WRAP> 
 </WRAP> </WRAP>
  
-<WRAP alert> +<WRAP center round box 100%> 
-**Cause:**\\   +**Cause:** QPLL or CLL does not lock due incorrect synthesis parameters.
-QPLL or CLL does not lock due frequency mismatch of reference clock. Reference clock frequency is not the one the CPLL or QPLL was set to handle forcing the VCO go out of range. +
-<WRAP tip> +
-**Identify:**\\ +
-Check reference clock generation settings.+
  
-**Fix:**\\ +**Identify:** Check channel and common util_adxcvr parameters against ones created with the transceiver wizard.
-Adjust setting of the clock chip to generate the correct frequency. +
-</WRAP> +
-</WRAP>+
  
 +**Fix:** Adjust synthesis parameters of the util_adxcvr component.
 </WRAP> </WRAP>
  
  
-<WRAP important> **Symptom:**\\ +<WRAP center round box 100%> 
-Link is DISABLED, In Linux boot log following appears:  **axi-adxcvr-tx: QPLL: failed to find setting for lane rate ...**+**Cause:** QPLL or CLL does not lock due frequency mismatch of reference clock. Reference clock frequency is not the one the CPLL or QPLL was set to handle forcing the VCO go out of range.
  
-<WRAP alert> +**Identify:** Check reference clock generation settings.
-**Cause:**\\ +
-QPLL can't find a configuration for desired lane rate with the given reference clock.+
  
-<WRAP tip> +**Fix:** Adjust setting of the clock chip to generate the correct frequency. 
-**Identify:**\\ +</WRAP>
-Check boot log. Check the required lane rate ref clock combination against the constraints defined in the transceiver manual. +
  
-**Fix:**\\ +----
-Configure the clock chip for different reference clock or switch to CPLL. +
  
-</WRAP> +====Link is DISABLED, In Linux boot log following appears:  axi-adxcvr-tx: QPLL: failed to find setting for lane rate ...==== 
-</WRAP> +<WRAP center round box 100%> 
-</WRAP>+**Cause:** QPLL can't find a configuration for desired lane rate with the given reference clock.
  
 +**Identify:** Check boot log. Check the required lane rate ref clock combination against the constraints defined in the transceiver manual.
  
 +**Fix:** Configure the clock chip for different reference clock or switch to CPLL.
 +</WRAP>
 +----
  
-<WRAP important> **Symptom:**\\ Link status stays in CGS and SYNC~ stays asserted+====Link status stays in CGS and SYNC~ stays asserted==== 
 +<WRAP center round box 100%> 
 +**Cause:** SYNC~ signal does not reach link layer hdl component
  
-<WRAP alert> +**Identify:** Check location constraints against schematic
-**Cause:**\\  SYNC~ signal does not reach link layer hdl component+
  
-<WRAP tip> +**Fix:** Adjust location constraints to match the schematic
-**Identify:**\\ +
-Check location constraints against schematic +
- +
-**Fix:**\\ +
-Adjust location constraints to match the schematic +
-</WRAP>+
 </WRAP> </WRAP>
  
-<WRAP alert> +<WRAP center round box 100%> 
-**Cause:**\\ SYNC~ signal polarity reversed+**Cause:** SYNC~ signal polarity reversed
  
-<WRAP tip> +**Identify:** Check constraints and schematic, look for any polarity inversion
-**Identify:**\\ +
-Check constraints and schematic, look for any polarity inversion+
  
-**Fix:**\\ +**Fix:** Adjust location constraints to match the schematic
-Adjust location constraints to match the schematic+
 </WRAP> </WRAP>
-</WRAP> 
- 
-<WRAP alert> 
-**Cause:**\\ JESD Rx can’t detect the CGS characters due different lane rate settings 
  
 +<WRAP center round box 100%>
 +**Cause:** JESD Rx can’t detect the CGS characters due different lane rate settings
  
-<WRAP tip> +**Identify:**
-**Identify:**\\+
   * Check if “Measured Link Clock” matches “Reported Link Clock” and “Lane Rate / 40”   * Check if “Measured Link Clock” matches “Reported Link Clock” and “Lane Rate / 40”
-  * Check is lane rate is as expected  +  * Check is lane rate is as expected 
-  * If OUTDIV_CLK is used for link clock adjust out-clk-select to match Lane Rate/ 40 +  * If OUTDIV_CLK is used for link clock adjust out-clk-select to match Lane Rate/ 40
   * If dedicated link clock is used adjust the external clock chip from device tree to output a clock of Lane Rate / 40   * If dedicated link clock is used adjust the external clock chip from device tree to output a clock of Lane Rate / 40
  
-**Fix:**\\ +**Fix:** Some general rules that always should hold:
-Some general rules that always should hold:+
   * <m>LaneRate = SampleRate * (10/8) * (M/L) * NP</m>   * <m>LaneRate = SampleRate * (10/8) * (M/L) * NP</m>
   * <m>SampleRate = DACrate / TotalInterpolation</m>   * <m>SampleRate = DACrate / TotalInterpolation</m>
   * <m>LinkClock = LaneRate/40</m>   * <m>LinkClock = LaneRate/40</m>
   * If OUTDIV_CLK is used: <m>LinkClock = RefClock/(OutClkSel==4 ? 2 : OutClkSel==3 ? 1 : 1)</m>   * If OUTDIV_CLK is used: <m>LinkClock = RefClock/(OutClkSel==4 ? 2 : OutClkSel==3 ? 1 : 1)</m>
-Where:  +Where:
   * M - //adi,converters-per-device//, device tree property from axi-jesd204-tx node   * M - //adi,converters-per-device//, device tree property from axi-jesd204-tx node
   * L - number of lanes per link, parameter of JESD IP   * L - number of lanes per link, parameter of JESD IP
   * NP - //adi,bits-per-sample// device tree property from axi-jesd204-tx node   * NP - //adi,bits-per-sample// device tree property from axi-jesd204-tx node
   * RefClock – reference clock for the transceivers   * RefClock – reference clock for the transceivers
-  * SampleRate - rate of sample that feeds the JESD link  +  * SampleRate - rate of sample that feeds the JESD link 
-  * DACrate – DAC raw sample rate after interpolation,  +  * DACrate – DAC raw sample rate after interpolation, 
-  * TotalInterpolation – product of selected interpolations on the datapath e.g dacInterpolation *channelInterpolation +  * TotalInterpolation – product of selected interpolations on the datapath e.g dacInterpolation *channelInterpolation
   * OutClkSel - //adi,out-clk-select// device tree property from xcvr node   * OutClkSel - //adi,out-clk-select// device tree property from xcvr node
 </WRAP> </WRAP>
-</WRAP> 
-</WRAP> 
  
-<WRAP important> **Symptom:**\\ Link status stays in DATA but output tone not as expected, raised noise floor  +---- 
-<WRAP alert> **Cause:**\\ Lane polarity inversion + 
-<WRAP tip> +====Link status stays in DATA but output tone not as expected, raised noise floor==== 
-**Identify:** Read received ILAS registers from DAC, in such case they do not make any sense compared to the LANEn_ILAS0..3 registers of the axi_jesd204_tx.     ILAS checksum mismatch. \\ +<WRAP center round box 100%> 
-**Fix:** For each in use lane adjust the corresponding bit in the TX_LANE_INVERT parameter of the util_adxcvr component to match any polarity inversion from the schematic  +**Cause:** Lane polarity inversion 
-</WRAP> + 
-</WRAP>+**Identify:** Read received ILAS registers from DAC, in such case they do not make any sense compared to the LANEn_ILAS0..3 registers of the axi_jesd204_tx. ILAS checksum mismatch. 
 + 
 +**Fix:** For each in use lane adjust the corresponding bit in the TX_LANE_INVERT parameter of the util_adxcvr component to match any polarity inversion from the schematic
 </WRAP> </WRAP>
  
-<WRAP important> **Symptom:**\\ Link status stays in DATA but output not as expected \\ +---- 
-E.g.: Expected signal is a ramp but actual is: + 
-{{ :resources:fpga:peripherals:jesd204:scramblingmismatch.png?direct&600 |}} +====Link status stays in DATA but output not as expected==== 
-<WRAP alert> **Cause:**\\ Mismatch in scrambling configuration.  +E.g.: For a Link Clock: 184.320 MHz; Nothing is transmitted from the transport layer but spectrum looks like below: 
-<WRAP tip> +{{ :resources:fpga:peripherals:jesd204:scrambling_mismatch_fft.jpg?nolink |}} 
-**Identify:** Check scrambling configuration registers from DAC against LINK_CONF1 config register SCRAMBLER_DISABLE bit of the link transmit peripheral. \\+<WRAP center round box 100%> 
 +**Cause:** Mismatch in scrambling configuration. 
 + 
 +**Identify:** Check scrambling configuration registers from DAC against LINK_CONF1 config register SCRAMBLER_DISABLE bit of the link transmit peripheral. 
 **Fix:** Adjust the above bits to match configuration. **Fix:** Adjust the above bits to match configuration.
-</WRAP> 
-</WRAP> 
  
 </WRAP> </WRAP>
 +----
 +
 +====Link status stays in DATA but output tone not as expected====
 +<WRAP center round box 100%>
 +**Cause:** Swapped lanes, source ‘Lane n’ connects to other than sink ‘Lane n’;
 +
 +**Identify:** Read received LID in the ILAS registers of the DAC, in such case they are out of order, permuted
  
-<WRAP important> **Symptom:**\\ Link status stays in DATA but output tone not as expected   
-<WRAP alert> **Cause:**\\ Swapped lanes, source ‘Lane n’ connects to other than sink ‘Lane n’;  
-<WRAP tip> 
-**Identify:** Read received LID in the ILAS registers of the DAC, in such case they are out of order, permuted\\ 
 **Fix:** Adjust link layer to physical layer connections in the FPGA block design through ad_xcvrcon procedure lane_map parameter; or \\Adjust crossbar from the DAC through the device tree nodes **Fix:** Adjust link layer to physical layer connections in the FPGA block design through ad_xcvrcon procedure lane_map parameter; or \\Adjust crossbar from the DAC through the device tree nodes
-</WRAP> 
 </WRAP> </WRAP>
  
-</WRAP>+----
  
 +====Link status stays in DATA but output tone not as expected, signal and its spectrum presents randomness====
 +
 +<WRAP center round box 100%>
 +**Cause:** Incorrect or missing constraint of the device clock (lane rate / 40)
 +
 +**Identify:** Report clocks of the transport layer, link layer component
  
-<WRAP important> **Symptom:**\\ Link status stays in DATA but output tone not as expected, signal and its spectrum presents randomness    
-<WRAP alert> **Cause:**\\ Incorrect or missing constraint of the device clock (lane rate / 40)   
-<WRAP tip> 
-**Identify:** Report clocks of the transport layer, link layer component\\ 
 **Fix:** In the constraints file define/create clocks with period that match desired lane rate / 40 **Fix:** In the constraints file define/create clocks with period that match desired lane rate / 40
-</WRAP> 
 </WRAP> </WRAP>
  
-</WRAP>+----
  
-<WRAP important> **Symptom:**\\ template+====SYSREF alignment error: Yes====
  
-<WRAP alert> 
-**Cause:**\\  template 
  
-<WRAP tip> +<WRAP center round box 100%> 
-**Identify:**\\ template+**Cause:**  frequency of SYSREF signal is not as expected
  
-**Fix:**\\ template+**Identify:** Check SYSREF generator parameters.
  
 +**Fix:** Set the frequency of SYSREF to be integer multiple of the reported local multiframe clock (LMFC)
 </WRAP> </WRAP>
 +
 +<WRAP center round box 100%>
 +**Cause:**  SYSREF signal sampling does not meet setup/hold requirements.
 +
 +**Identify:** Check if SYSREF path is constrained.
 +
 +**Fix:** Define timing constraints for SYSREF in edge aligned source synchronous interface mode and adjust device clock and SYSREF phase from the clock chip accordingly.
 </WRAP> </WRAP>
 +
 +----
 +
 +==== Template ====
 +<WRAP center round box 100%>
 +**Cause:**  template
 +
 +**Identify:** template
 +
 +**Fix:** template
 </WRAP> </WRAP>
 +----
  
 ===== More Information ===== ===== More Information =====
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 ===== Support ===== ===== Support =====
 Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[https://ez.analog.com/community/fpga|EngineerZone]]. Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[https://ez.analog.com/community/fpga|EngineerZone]].
 +
 +~~NOTOC~~
  
resources/fpga/peripherals/jesd204/jesd204_troubleshooting.txt · Last modified: 20 Dec 2021 08:19 by Laszlo Nagy

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