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--- resources:fpga:peripherals:jesd204:jesd204_troubleshooting [05 Mar 2021 12:35] – [Link status stays in CGS and SYNC~ de-asserts, subclass 1] Laszlo Nagy
+++ resources:fpga:peripherals:jesd204:jesd204_troubleshooting [20 Dec 2021 08:09] – [Link status stays in CGS and SYNC~ de-asserts, subclass 1] Laszlo Nagy
@@ Line 63: / Line 63: @@
 </WRAP>
+----
+====Link is DISABLED, In Linux boot log following appears:  axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 set lane rate 16500000 kHz failed (-22) ...====
+<WRAP center round box 100%>
+**Cause:** QPLL can't find a configuration for desired lane rate with the given reference clock.
+**Identify:** Check boot log. Check the required lane rate ref clock combination against the constraints defined in the transceiver manual.
+**Fix:** Configure the clock chip for different reference clock or switch to CPLL or QPLL0/1.
+</WRAP>
 ----
@@ Line 119: / Line 129: @@
 ----
-====Link status stays in CGS and SYNC~ de-asserts, subclass 1====
+====Link status stays in CGS and SYNC~ is de-asserts====
+<WRAP center round box 100%>
+**Cause:**  SYNC~ signal not connected correctly, pulled high
+**Identify:**
+#jesd_status
+or
+#grep "" /sys/bus/platform/devices/*.axi-jesd*/status*
+  Link status: CGS
+  SYNC~: deasserted
+**Fix:** Make sure SYNC~ is connected to the Link Transmit peripheral and is property driven.
+</WRAP>
 <WRAP center round box 100%>
-**Cause:**  Missing SYSREF at peripheral
+**Cause:**  Missing SYSREF at peripheral in subclass 1
 **Identify:**

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