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--- resources:fpga:peripherals:jesd204:jesd204_troubleshooting [05 Mar 2021 12:35] – [Link status stays in CGS and SYNC~ de-asserts, subclass 1] Laszlo Nagy
+++ resources:fpga:peripherals:jesd204:jesd204_troubleshooting [22 Apr 2021 08:36] – [Link is DISABLED, In Linux boot log following appears: axi-adxcvr-tx: QPLL: failed to find setting for lane rate ...] Laszlo Nagy
@@ Line 63: / Line 63: @@
 </WRAP>
+----
+====Link is DISABLED, In Linux boot log following appears:  axi-jesd204-tx 44b90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 set lane rate 16500000 kHz failed (-22) ...====
+<WRAP center round box 100%>
+**Cause:** QPLL can't find a configuration for desired lane rate with the given reference clock.
+**Identify:** Check boot log. Check the required lane rate ref clock combination against the constraints defined in the transceiver manual.
+**Fix:** Configure the clock chip for different reference clock or switch to CPLL or QPLL0/1.
+</WRAP>
 ----

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