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resources:fpga:peripherals:jesd204:jesd204_tpl_dac [06 May 2021 09:36] – [Restrictions] Laszlo Nagyresources:fpga:peripherals:jesd204:jesd204_tpl_dac [26 Oct 2021 12:23] (current) – Added link to HDL User Guide and removed footer Adrian Costina
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 The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map. The peripheral can be configured at runtime through a AXI4-Lite memory mapped register map.
 +
  
 ===== Features ===== ===== Features =====
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   * Per-channel dual-tone DDS (optional)   * Per-channel dual-tone DDS (optional)
   * Runtime re-configurability through memory-mapped register interface (AXI4-Lite)   * Runtime re-configurability through memory-mapped register interface (AXI4-Lite)
 +
  
 ===== Files ===== ===== Files =====
 +
 [[github>hdl?master/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v|ad_ip_jesd204_tpl_dac.v]] [[github>hdl?master/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v|ad_ip_jesd204_tpl_dac.v]]
 +
  
 ===== Block Diagram ===== ===== Block Diagram =====
  
 {{ :resources:fpga:docs:ad_ip_jesd204_transport_dac.png |}} {{ :resources:fpga:docs:ad_ip_jesd204_transport_dac.png |}}
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 ===== Synthesis Configuration Parameters ===== ===== Synthesis Configuration Parameters =====
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 | ''DDS_CORDIC_PHASE_DW'' | CORDIC DDS Phase Width | 16 | | ''DDS_CORDIC_PHASE_DW'' | CORDIC DDS Phase Width | 16 |
 | ''DATAPATH_DISABLE'' | Disable instantiation of DDS core. | 0 | | ''DATAPATH_DISABLE'' | Disable instantiation of DDS core. | 0 |
 +
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
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 | ''dac_ddata'' | Input  | Raw application layer data, every channel concatenated.  | | ''dac_ddata'' | Input  | Raw application layer data, every channel concatenated.  |
 | ''dac_dunf'' | Input  | Application layer underflow. | | ''dac_dunf'' | Input  | Application layer underflow. |
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 {{page>:resources:fpga:docs:hdl:regmap##DAC Channel (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##DAC Channel (axi_ad*)&nofooter&noeditbtn}}
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 ===== Theory of Operation ===== ===== Theory of Operation =====
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 === Application layer interface === === Application layer interface ===
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 The application layer connects to the framer block when the DMA source is selected. The framer module takes sample data and maps it onto the format that the JESD204 link expects for the specified framer configuration. The application layer connects to the framer block when the DMA source is selected. The framer module takes sample data and maps it onto the format that the JESD204 link expects for the specified framer configuration.
  
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 The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.
 +
 +=== External synchronization ===
 +
 +By setting the ''EXT_SYNC'' parameter of the IP to 1 an external synchronization signal ''dac_sync_in'' can be used to trigger data movement from user application layer to the link layer,  reset internal DDS cores or PRBS generators. 
 +If the ''EXT_SYNC'' parameter is set to zero the external signal is ignored and only a software controlled reset happens inside the DDS,PRBS logic. 
 +
 +The external synchronization signal should be synchronous with the dac clock. Synchronization will be done on the rising edge of the signal. 
 +
 +The self clearing ''SYNC'' control bit from the ''REG_CNTRL_1'' (''0x44'') register will arm the trigger logic to wait for the external sync signal. The ''DAC_SYNC_STATUS'' status bit from the ''REG_SYNC_STATUS'' (''0x68'') register will show that the synchronization is armed but the synchronization signal has not yet been received.
 +
 +Once the sync signal is received the data will start to flow and the ''DAC_SYNC_STATUS'' status bit will reflect that with a deassertion. 
 +
 +While the synchronization mechanism is armed the ''dac_valid'' output signal is gated until the trigger signal is received. The gating happens only during this period, meaning that ''dac_valid'' will stay high in all other cases (normal operation). 
  
  
 ===== Restrictions ===== ===== Restrictions =====
 +
 Reduced number of octets-per-frame (''F'') settings. The following values are supported by the peripheral: 1, 2, 4\\   Reduced number of octets-per-frame (''F'') settings. The following values are supported by the peripheral: 1, 2, 4\\  
   * Starting from [[repo>hdl/commit/454b900f90081fb95be857114e768f662178c8bd|this]] commit this restriction no longer applies    * Starting from [[repo>hdl/commit/454b900f90081fb95be857114e768f662178c8bd|this]] commit this restriction no longer applies 
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 <note important>To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B/C software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.</note> <note important>To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B/C software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.</note>
 +
  
 ===== Supported Devices ===== ===== Supported Devices =====
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 {{page>:resources:fpga:peripherals/jesd204##jesd204bc_mixed-signal_front_ends&nofooter&noeditbtn}} {{page>:resources:fpga:peripherals/jesd204##jesd204bc_mixed-signal_front_ends&nofooter&noeditbtn}}
    
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 ===== More Information ===== ===== More Information =====
  
   * [[:resources:fpga:peripherals:jesd204| JESD204 Interface Framework]]   * [[:resources:fpga:peripherals:jesd204| JESD204 Interface Framework]]
   * [[:resources:fpga:peripherals:jesd204:jesd204_glossary| Glossary of terms]]   * [[:resources:fpga:peripherals:jesd204:jesd204_glossary| Glossary of terms]]
 +  * [[../../docs/hdl| HDL User Guide]]
 +
  
 ===== Technical Support ===== ===== Technical Support =====
  
 Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]]. Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the [[ez>community/fpga|EngineerZone]].
 +
resources/fpga/peripherals/jesd204/jesd204_tpl_dac.1620286571.txt.gz · Last modified: 06 May 2021 09:36 by Laszlo Nagy

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