Differences

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--- resources:fpga:peripherals:jesd204:jesd204_glossary [07 Feb 2022 12:28] – [Clocks] Laszlo Nagy
+++ resources:fpga:peripherals:jesd204:jesd204_glossary [07 Feb 2022 12:30] (current) – [Clocks] Laszlo Nagy
@@ Line 44: / Line 44: @@
 | **conversion clock** | Clock used by a converter device to perform the A2D or D2A conversion.  |
 | **link clock** | Link parallel clock feeding the link layer, lane rate / 40 or lane rate / 80 for 204B links, lane rate / 66 for 204C 64b66b links |
-| **device clock** | Master clock supplied to the JESD204B device from which all other clock signals must be derived. In context of FPGA is an integer multiple of frame clock, used directly in transport and application layers. |
+| **device clock** | Master clock supplied to the JESD204B device from which all other clock signals must be derived. In context of FPGA is an integer multiple of frame clock, used directly in link, transport and application layers. |
 | **frame clock** | Clock rate at which samples are generated/processed. Has the same rate as the conversion clock, except for interpolating DACs or decimating DACs, where it is slower by the interpolation/decimation factor.  |
 | **line clock** | Clock for the high-speed serial interface. |

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