The CN0363 Sequencer FPGA Peripheral is part of the EVAL-CN0363-PMDZ HDL reference design and is responsible to sequence the various data channels to the DMA.
|cn0363_dma_sequencer.v||Verilog source for the peripheral.|
|cn0363_dma_sequencer_ip.tcl||TCL script to generate the Vivado IP-integrator project for the peripheral.|
| ||Clock||All other signals are synchronous to this clock.|
| ||Synchronous active low reset||Resets the internal state machine of the core.|
| ||AXI-Stream slave||Phase data channel.|
| ||AXI-Stream slave||Sample data channel.|
| ||AXI-Stream slave||Filtered sample data channel.|
| ||AXI-Stream slave||Demodulated I/Q sample data channel.|
| ||AXI-Stream slave||Filtered demodulated I/Q sample data channel.|
| ||FIFO Write Interface master||Low-level SPI bus interface that is controlled by peripheral.|
| ||Output||The overflow signal is asserted if a overflow on the DMA interface is detected.|
| ||Input||Data channel enable sequencer output enable.|
| ||Output||Reset signal for the processing pipeline|
The CN0363 DMA sequencer core acts as a link between the CN0363 processing pipeline and the connected DMA controller. On one side it accepts data from the processing pipeline and on the other side it sends the data to the DMA controller. The core is only active when the DMA controller signals that it is waiting for data, when it is inactive it also asserts the
processing_resetn signal to keep the processing pipeline in reset. Since the DMA is running at a much faster clock than the output data rate from the processing pipeline the different channels are time-division-multiplexed and send one by one to the DMA controller over the
When active the core cycles through the input channels in the following order.
Each of these has a corresponding bit in the
channel_enable and only if the bit is set the channel is sent to the
dma_wr interface, otherwise it is discarded. This allows an application to select which data channels it wants to capture.