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resources:fpga:docs:util_var_fifo [06 Jun 2018 12:58]
Adrian Costina Reviewed
resources:fpga:docs:util_var_fifo [14 Jan 2021 05:38]
Robin Getz use wiki interwiki links
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 ==== Detailed Description ==== ==== Detailed Description ====
  
-This IP controls ​and external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.+This IP controls ​an external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.
  
 ==== Design Guidelines ==== ==== Design Guidelines ====
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 ==== References ==== ==== References ====
   * [[https://​github.com/​analogdevicesinc/​hdl/​tree/​master/​library/​util_var_fifo| UTIL_VAR_FIFO IP source code]] \\   * [[https://​github.com/​analogdevicesinc/​hdl/​tree/​master/​library/​util_var_fifo| UTIL_VAR_FIFO IP source code]] \\
-  * [[https://​wiki.analog.com/​resources/​fpga/​docs/​arch | ADI Reference designs architecture ]] \\+  * [[/​resources/​fpga/​docs/​arch | ADI Reference designs architecture ]] \\
  
 {{navigation #axi_ip|AXI IP#hdl|Main page#​tips|Tips}} {{navigation #axi_ip|AXI IP#hdl|Main page#​tips|Tips}}
resources/fpga/docs/util_var_fifo.txt · Last modified: 14 Jan 2021 05:38 by Robin Getz