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The most recent version of this page is a draft.DiffThis version is outdated by a newer approved version.DiffThis version (10 Aug 2016 17:04) was approved by Andrei Grozav.

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Table of Contents

UTIL_RFIFO

UTIL_RFIFO is a core design to manage the communication between the DMA core and the DAC core by handling the data rate differences of the two cores.

Features

  • Supports Altera and Xilinx devices.
  • Works with a faster DAC clock than the DMA clock
  • Can be used for devices have multiple channels (max eight channels)
  • Handles communication between DAC and DMA cores that have different bus widths

Timing diagram

After initialization or a transmission restart, the first fifo depth number of samples will not be valid. This is because the input data is written into memory and output data is read from the same memory, before input data is written, resulting the first data being read from uninitialized memory cells.

Parameters

Name Description Default Value
NUM_OF_CHANNELS The number of communication channels sported to be supported. 4
DIN_DATA_WIDTH The bus width of the input data (DMA bus width). 32
DOUT_DATA_WIDTH The bus width of the output data (DAC bus width). 64
DIN_ADDRESS_WIDTH The address width for the input data. 4

Interface

Interface Pin Type Description
din_0 Input interface 0
din_enable_0 Output Enable
din_valid_0 Output Valid
din_data_0 Input Data
din_1 Input interface 1
din_enable_1 Output Enable
din_valid_1 Output Valid
din_data_1 Input Data
… …
din_7 Input interface 7
din_enable_7 Output Enable
din_valid_7 Output Valid
din_data_7 Input Data
din_unf Input data underflow
din_unf input Input data underflow
dout_unf Output data underflow
dout_unf output Output data underflow
  • The bus width of the output data buses must always be greater or equal with the width of the input data buses.
  • The number of I/O channels that the Rfifo can handle is limited to eight.
resources/fpga/docs/util_rfifo.1470841415.txt.gz · Last modified: 10 Aug 2016 17:03 by Andrei Grozav

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