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resources:fpga:docs:hdl:xcomm2ip [19 Aug 2016 17:52] – rejeesh kuttyresources:fpga:docs:hdl:xcomm2ip [20 Aug 2016 05:21] (current) – rejeesh kutty
Line 378: Line 378:
 ++++ ++++
  
-<fc #800000>How do I send my own data to the ADI IP core?</fc>+<fc #800000>**How do I send my own data to the ADI IP core?**</fc>
  
 This is NOT something we can answer. It is also a question of "what" than "how". The "how" part is that you either generate the data in hardware or in software. As for the "what", note that the most of the interface cores are meant to for analog data. That is, though it is a digital interface, the data must be and considered to be analog. An often asked question is why the data one sent to the DAC does not match the data received at the ADC. This is a mis-conception, the digital data to the DAC is must be and in fact a "digitized" analog signal. The "data" in its commonly used sense, must be encoded and modulated before passing it to the analog domain. This is NOT something we can answer. It is also a question of "what" than "how". The "how" part is that you either generate the data in hardware or in software. As for the "what", note that the most of the interface cores are meant to for analog data. That is, though it is a digital interface, the data must be and considered to be analog. An often asked question is why the data one sent to the DAC does not match the data received at the ADC. This is a mis-conception, the digital data to the DAC is must be and in fact a "digitized" analog signal. The "data" in its commonly used sense, must be encoded and modulated before passing it to the analog domain.
Line 385: Line 385:
  
 ===== Modifying and customizing ADI projects  ===== ===== Modifying and customizing ADI projects  =====
-<fc #800000>How do I insert a custom AXI IP core inside an ADI project?</fc>+<fc #800000>**How do I insert a custom AXI IP core inside an ADI project?**</fc> 
 + 
 +As mentioned above, the RFBBP AXI core is designed for the "fmcomms2" projects and is to be placed next to the "axi_ad9361" core. In order to do this, we need to modify the "fmcomms2" project. This can be easily done using the ADI TCL frame work. We create this as a new project inheritting the "fmcomms2" board design and doing the necessary customizations. In the RFBBP design, this is all done using a single TCL file. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +[~/rfbbp]> mkdir zc706 
 +[~/rfbbp]> cd zc706 
 +[~/rfbbp/zc706]> touch zc706.tcl 
 +[~/rfbbp/zc706]> touch Makefile 
 +</xterm> 
 +++++ 
 + 
 +Lets look at the "zc706.tcl" file contents. In order to use the ADI frame work we need to source the TCL procedures. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +set ad_hdl_dir $::env(ADI_HDL_DIR) 
 +set ad_phdl_dir $::env(ADI_HDL_DIR) 
 + 
 +source $ad_hdl_dir/projects/scripts/adi_board.tcl 
 +source $ad_hdl_dir/projects/scripts/adi_project.tcl 
 +</xterm> 
 +++++ 
 + 
 +Then we set the "zynq" flag and create the new project. Set the board part for the predefined settings.  
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +set sys_zynq 1 
 + 
 +create_project zc706 . -part xc7z045ffg900-2 -force 
 + 
 +set_property board_part xilinx.com:zc706:part0:1.2 [current_project] 
 +</xterm> 
 +++++ 
 + 
 +Now, pay special attention, we set the ip repository folders. The default ADI library and the "ip" library we created above for the "axi_xcomm2ip" core. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +set_property ip_repo_paths [list $ad_hdl_dir/library ../ip]  [current_fileset] 
 + 
 +update_ip_catalog 
 +</xterm> 
 +++++ 
 + 
 +Once the libraries are read, we can inherit the "fmcomms2" board design and customize it. The board design is inherited by simply sourcing the carrier (zc706) and the fmc (fmcomms2) board. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +create_bd_design "system" 
 +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl 
 +source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl 
 +</xterm> 
 +++++ 
 + 
 +The customization, inserting the "axi_xcomm2ip", requires us to remove the existing connection at the "axi_ad9361" DAC interface. This can be done by removing the nets connected to the "axi_ad9361" DAC interface ports using the "delete_bd_objs" command. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i0]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i0]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q0]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q0]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_i1]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_i1]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_valid_q1]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_data_q1]]] 
 +delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_ad9361/dac_dunf]]] 
 +</xterm> 
 +++++ 
 + 
 +Add the "axi_xcomm2ip" core. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +set axi_xcomm2ip [create_bd_cell -type ip -vlnv analog.com:user:axi_xcomm2ip:1.0 axi_xcomm2ip] 
 +set_property -dict [list CONFIG.XCOMM2IP_1T1R_OR_2T2R_N {0}] $axi_xcomm2ip 
 +</xterm> 
 +++++ 
 + 
 +Connect its slave AXI interface to the "ps7" with an address map of 0x79040000. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +ad_cpu_interconnect 0x79040000 axi_xcomm2ip 
 +</xterm> 
 +++++ 
 + 
 +And the data path connections; clock, reset, ADC and DAC interfaces. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +ad_connect  axi_ad9361/clk axi_xcomm2ip/clk 
 +ad_connect  axi_ad9361/rst axi_xcomm2ip/rst 
 +ad_connect  axi_ad9361/adc_valid_i0 axi_xcomm2ip/adc_valid_i0 
 +ad_connect  axi_ad9361/adc_data_i0 axi_xcomm2ip/adc_data_i0 
 +ad_connect  axi_ad9361/adc_valid_q0 axi_xcomm2ip/adc_valid_q0 
 +ad_connect  axi_ad9361/adc_data_q0 axi_xcomm2ip/adc_data_q0 
 +ad_connect  axi_ad9361/adc_valid_i1 axi_xcomm2ip/adc_valid_i1 
 +ad_connect  axi_ad9361/adc_data_i1 axi_xcomm2ip/adc_data_i1 
 +ad_connect  axi_ad9361/adc_valid_q1 axi_xcomm2ip/adc_valid_q1 
 +ad_connect  axi_ad9361/adc_data_q1 axi_xcomm2ip/adc_data_q1 
 +ad_connect  axi_xcomm2ip/dac_valid_i0 axi_ad9361/dac_valid_i0 
 +ad_connect  axi_xcomm2ip/dac_data_i0 axi_ad9361/dac_data_i0 
 +ad_connect  axi_xcomm2ip/dac_valid_q0 axi_ad9361/dac_valid_q0 
 +ad_connect  axi_xcomm2ip/dac_data_q0 axi_ad9361/dac_data_q0 
 +ad_connect  axi_xcomm2ip/dac_valid_i1 axi_ad9361/dac_valid_i1 
 +ad_connect  axi_xcomm2ip/dac_data_i1 axi_ad9361/dac_data_i1 
 +ad_connect  axi_xcomm2ip/dac_valid_q1 axi_ad9361/dac_valid_q1 
 +ad_connect  axi_xcomm2ip/dac_data_q1 axi_ad9361/dac_data_q1 
 +ad_connect  axi_xcomm2ip/dac_dovf axi_ad9361/dac_dovf 
 +ad_connect  axi_xcomm2ip/dac_dunf axi_ad9361/dac_dunf 
 + 
 +ad_connect  util_ad9361_dac_upack/dac_data_0 axi_xcomm2ip/dma_data_i0 
 +ad_connect  util_ad9361_dac_upack/dac_data_1 axi_xcomm2ip/dma_data_q0 
 +ad_connect  util_ad9361_dac_upack/dac_data_2 axi_xcomm2ip/dma_data_i1 
 +ad_connect  util_ad9361_dac_upack/dac_data_3 axi_xcomm2ip/dma_data_q1 
 +ad_connect  axi_ad9361_dac_dma/fifo_rd_underflow axi_xcomm2ip/dma_dunf 
 +ad_connect  axi_xcomm2ip/dma_dovf GND 
 +</xterm> 
 +++++ 
 + 
 +Some clean-up, saving and validating. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +delete_bd_objs [get_bd_cells ila_adc] 
 +delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd] 
 + 
 +regenerate_bd_layout 
 +save_bd_design 
 +validate_bd_design 
 +</xterm> 
 +++++ 
 + 
 +Generate all the targets, create the top level wrapper and add the reset of the files. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +generate_target {synthesis implementation} [get_files zc706.srcs/sources_1/bd/system/system.bd] 
 +make_wrapper -files [get_files zc706.srcs/sources_1/bd/system/system.bd] -top 
 +import_files -force -norecurse -fileset sources_1 zc706.srcs/sources_1/bd/system/hdl/system_wrapper.v 
 + 
 +adi_project_files zc706 [list \ 
 +  "$ad_hdl_dir/library/common/ad_iobuf.v" \ 
 +  "$ad_hdl_dir/projects/fmcomms2/zc706/system_top.v" \ 
 +  "$ad_hdl_dir/projects/fmcomms2/zc706/system_constr.xdc"\ 
 +  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] 
 +</xterm> 
 +++++ 
 + 
 +Now build the project. 
 +++++ Show/Hide Commands: | 
 +<xterm> 
 +adi_project_run zc706 
 +</xterm> 
 +++++
  
 ===== Building Linux ===== ===== Building Linux =====
Line 393: Line 540:
 ===== Accessing the HDL IP core in Linux ===== ===== Accessing the HDL IP core in Linux =====
 === How do I access a HDL IP core from Linux? === === How do I access a HDL IP core from Linux? ===
 +
  
  
resources/fpga/docs/hdl/xcomm2ip.txt · Last modified: 20 Aug 2016 05:21 by rejeesh kutty

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