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|===== Resource utilization ===== 



==== ad40xx_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48      ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
|5835 (10.97%) | 7907 (7.43%) | 9 (4.09%) | 6 (4.29%) | 0   | 6   | 2   | 0  |
</WRAP>

==== ad5758_sdz_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT          ^FD          ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
|3978 (7.48%) |5291 (4.97%)| 9 (4.09%)| 2 (1.43%) | 0   | 5    | 2   | 0 |
</WRAP>

==== ad5766_sdz_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD           ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
|5837(10.97%%) | 8103 (7.62%)| 9 (4.09%)| 3 (2.14%)| 0   | 5    | 2   | 0  |
</WRAP>
==== ad6676evb_vc707 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48      ^RAMB/FIFO     ^URAM ^BUFG* ^MMCM ^PLL |
|42003 (13.83%) | 47152 (7.77%) | 4  (0.14%)| 150 (14.56%) | 0   |13   | 3    | 1  |
</WRAP>

==== ad6676evb_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD             ^DSP48  ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 8547 (3.91%) | 11833 (2.71%) | 9 (1%) | 4 (0.73%) | 0   | 6    | 2   | 0  |
</WRAP>

==== ad7134_fmc_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD           ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 6085 (11.44%)|8421 (7.91%) | 9 (4.09%)|6 (4.29%) | 0   | 7    | 3   | 0  |
</WRAP>

==== ad738x_fmc_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD           ^DSP48    ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 5715 (10.74%) | 7508 (7.06%)|9 (3.12%)|3 (2.14%) | 0   | 5    | 2   | 0  |
</WRAP>

==== ad7405_fmc_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48      ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5798 (10.9%) | 7536 (7.08)  | 9 (4.09%) | 3 (2.14%) | 0   | 7   | 3  | 0  |  
</WRAP>

==== ad7616_sdz_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD           ^DSP48     ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 5743 (10.8%) |7471 (7.02%) | 9 (3.12%)| 3 (2.14%)  | 0   | 5    | 2   | 0  |  
</WRAP>

==== ad7616_sdz_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48  ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5033 (2.3%)  | 6759 (1.55%) |9 (1%) | 3 (0.55%) | 0   | 5    | 2   | 0  |
</WRAP>

==== ad77681evb_cora7s ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD             ^DSP48  ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 2495 (17.33%)| 3179 (11.04%) |0      | 1 (2%)   | 0   | 1    | 0   | 0  |
</WRAP>

==== ad77681evb_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 5719 (10.75%)| 7485 (7.03%) | 9 (4.09%)|3 (2.14%) | 0   | 6   | 2   | 0  | 
</WRAP> 

==== ad7768evb_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5798 (10.9%) | 8818 (8.29%) | 9 (4.09%)| 3 (2.14%) | 0   | 6    | 2   | 0  |
</WRAP>

==== ad9208_dual_ebz_vcu118 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48    ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 56686 (4.79%)| 82635 (3.49%)| 7 (0.1%)| 302 (13.98%)| 0   | 12   | 1   | 6  |
</WRAP>

==== ad9265_fmc_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 5042 (2.31%) | 7340 (1.68%) | 1 (1.11%)| 3 (0.55%)| 0   | 6    | 2   | 0  |
</WRAP>

==== ad9434_fmc_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT          ^FD            ^DSP48   ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5032 (2.3%) | 7019 (1.61%) | 9 (1%) | 3 (0.55%) | 0   | 8    | 3   | 0  |
</WRAP>

==== ad9467_fmc_kc705 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 27636 (13.56%) | 29107 (7.14%) | 4 (0.48%)| 49 (11.01%)| 0   | 10   | 2   | 1  |
</WRAP>

==== ad9467_fmc_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD          ^DSP48      ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5701 (10.72%)|7774 (7.31%)| 9 (4.09%) | 3 (2.14%) | 0   | 6    | 2   | 0  |
</WRAP>

==== ad9739a_fmc_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD           ^DSP48         ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 12140(5.55%) | 18343 (4.2%) | 169 (18.78%) | 6 (1.1%) | 0   | 7    | 2   | 0  |
</WRAP>

==== ad_fmclidar1_ebz_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48   ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 12053 (5.51%)| 16111 (3.68%)| 9 (1%) | 8 (1.47%) | 0   | 6   | 2   | 0  |
</WRAP>

==== ad_fmclidar1_ebz_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD             ^DSP48 ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 9550 (3.48%) | 13114 (2.39%) | 0    | 6 (0.66%) | 0   | 1    | 0   | 0  |
</WRAP>

==== adaq7980_sdz_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48      ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 5617 (10.56%) | 7519 (7.07%) | 9 (4.09%) | 3 (2.14%) | 0   | 5    | 2   | 0  |
</WRAP>


==== adrv9009_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD              ^DSP48         ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 51182 (23.41%)| 67032 (15.33%) | 157 (17.44%) | 44 (7.98%) | 0  | 18   | 7   | 1  |
</WRAP>
==== adrv9009_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48        ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 32089 (11.71%)| 48395 (8.83) | 144 (5.71%) | 522 (57.24%)| 0   | 6  |  3  |  3  |
</WRAP>

==== adrv9009zu11eg_adrv2crr_fmc ==== 
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48     ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 58408 (19.56%)| 73762 (12.35%)| 35 (1.2%)|101 (16.83%)| 0   | 8    | 2   | 4  |
</WRAP>




==== adrv9361z7035_ccbob_cmos ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48       ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 12846 (7.47%) | 20956 (6.1%) | 28 (3.11%) | 4 (0.8%) | 0   | 8    | 0   | 0  |
</WRAP>

==== adrv9361z7035_ccbob_lvds ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48       ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 12739 (7.41%) | 20916 (6.08%) | 28 (3.11%) | 4 (0.8 %) | 0   | 8    | 0   | 0  |
</WRAP>

==== adrv9361z7035_ccpackrf_lvds ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD           ^DSP48      ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 12222 (7.11%) | 19603 (5.7%)| 28 (1.96%)| 4 (0.8%) | 0   | 5    | 1   | 0  |
</WRAP>

==== adrv9361z7035_ccfmc_lvds ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48       ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 15163 (8.82%) | 24480 (7.12%) | 37 (4.11%) | 6 (1.2%) | 0   | 15   | 3   | 0  |
</WRAP>

==== adrv9364z7020_ccbob_cmos ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD               ^DSP48       ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 8783 (16.51%) | 14178 (13.33%)  |  14 (6.36%)| 4 (2.86%) | 0   | 4    | 0   | 0  |
</WRAP>

==== adrv9364z7020_ccbob_lvds ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48       ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 8742 (16.43%) | 14147 (13.35) | 14 (6.36%) | 4 (2.86%)| 0   | 4    | 0   | 0  |
</WRAP>

==== adrv9364z7020_ccpackrf_lvds ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48       ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 8845 (16.63%) | 14120 (13.27) | 14 (6.36%) | 4 (2.86%) | 0   | 5    | 1   | 0  |
</WRAP>

==== adrv9371x_kcu105 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48        ^RAMB/FIFO     ^URAM ^BUFG* ^MMCM ^PLL |
| 71151 (29.6%) |98416 (20.47) | 151 (7.86%) | 313 (52.08%) | 0   | 19   | 5   | 8  |
</WRAP>

==== adrv9371x_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD              ^DSP48      ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 51403 (23.51%) | 66585 (15.23%) |157 (17.44%)| 44 (8%)  | 0   | 18   | 7   | 1  |
</WRAP>

==== adrv9371x_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48        ^RAMB/FIFO     ^URAM ^BUFG* ^MMCM ^PLL |
| 32942 (12.02%) | 47272 (8.62%) | 144 (5.71%) | 464 (50.88%) | 0   | 6    | 3   | 3  |
</WRAP>

==== adv7511_zc702 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48      ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 3259 (6.13%) | 4658 (4.38%) | 9 (4.09%) | 2 (1.43%) | 0   | 5    | 2   | 0  |
</WRAP>

==== adv7511_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD          ^DSP48   ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 3218 (1.47%)| 4526 (1.04%) | 9 (1%) | 2 (0.37%) | 0   | 5    | 2  |  0  |
</WRAP>

==== adv7511_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48      ^RAMB/FIFO  ^URAM   ^BUFG* ^MMCM ^PLL |
| 3985 (7.49%)| 5291 (4.97%)  | 9 (4.09%) | 2 (1.43%) | 0     | 5    | 2   |  0 |
</WRAP>

==== cn0363_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48       ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 7559 (14.21%) | 10851 (10.2%) | 13 (5.91%) | 10 (6.79%) | 0   | 5    | 2  | 0   |
</WRAP>

==== dac_fmc_ebz_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48       ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 19657 (8.99%) | 23584 (5.39%) | 25 (2.78%) | 70 (12.84%)| 0   | 6    | 2   | 0  |
</WRAP>

==== dac_fmc_ebz_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48       ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 17086(6.23%) | 20102 (3.67%) | 16 (0.63%) | 36 (3.95%) | 0   | 0    | 0   | 0  |
</WRAP>
==== daq2_kc705 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48       ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 53829 (26.41%) | 59392 (14.57%)| 20 (2.38%) |311 (69.89%)| 0   | 11   | 2   | 1  |
</WRAP>

==== daq2_kcu105 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD            ^DSP48     ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 65627 (27.07%) | 83877 (17.3%)| 23 (1.2%)|340 (56.58%) | 0   | 12   | 2   | 5  | 
</WRAP>


==== daq2_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48      ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 46696 (21.36%) | 54866 (12.55%)| 25 (2.78%)| 281 (51.47%)| 0   | 11   | 4   | 1  |
</WRAP>

==== daq2_zcu102====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48      ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 27376 (9.99%) | 33742 (6.16%) | 16 (0.63%)|519 (56.91%)| 0   | 0    | 0   | 0  |
</WRAP>

==== daq3_kcu105 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48    ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 60912 (25.13%) | 80223 (16.55%)|23 (1.2%)|340(56.58%) | 0   | 12   | 2   | 5  |
</WRAP>

==== daq3_vcu118 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD         ^DSP48     ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 61368 (5.19%)|80422(3.4%)|23 (0.34%)|434 (20.16%)| 0   | 12   | 1   | 6  |
</WRAP>

==== daq3_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD            ^DSP48      ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 42318 (19.36%) |50632 (11.585)| 25 (2.78%)| 282 (51.65%)| 0   | 11   | 4  | 1  | 
</WRAP>

==== daq3_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48      ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 22637 (8.26%) | 28738 (5.24%)| 16 (0.63%)|264 (28.95%)| 0   | 1    | 1   | 1  |
</WRAP>

==== fmcadc2_vc707 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48      ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 46610 (15.35%) | 52634 (8.67%) | 4 (32.49%)| 668 (64.85%)| 0   | 13   | 3  | 1  |
</WRAP>

==== fmcadc2_zc706====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD           ^DSP48   ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 28662 (13.11%) |34662 (7.39%)| 9 (1%) | 27 (4.86%) | 0   | 10   | 4   | 1  |
</WRAP>



==== fmcadc5_vc707 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48      ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 58272 (19.19%) |67842 (11.17%) | 36 (1.29%)| 683 (66.31%)| 0   | 14   | 3   | 1  |  
</WRAP>

==== fmcjesdadc1_kc705 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD           ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 35009 (17.18%) |39735 (9.75%)| 4 (0.48%)|66 (14.83%)| 0   | 10   | 2   | 1  |
</WRAP>

==== fmcjesdadc1_vc707 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD           ^DSP48     ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 44817 (14.76%) |51482 (8.48%)| 4 (0.14%)| 158 (15.34%)| 0   | 13   | 3   | 1  |
</WRAP>

==== fmcjesdadc1_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD            ^DSP48  ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 11301 (5.17%)|15463 (3.54%) | 9 (1%)|6 (1.1%) | 0    | 6    | 2   | 0  |
</WRAP>

==== fmcomms11_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48      ^RAMB/FIFO     ^URAM ^BUFG* ^MMCM ^PLL |
| 56873(26.02%) | 65949(15.08%) | 41 (4.56%)| 287 (52.57%) | 0   | 11    | 4  | 1  |
</WRAP>

==== fmcomms2_kc705 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48     ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 36828 (18.07%)| 44647 (10.95%)|32 (3.81%)| 52 (11.69%)| 0   | 11   | 2   | 1  |
</WRAP>

==== fmcomms2_kcu105 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD            ^DSP48     ^RAMB/FIFO(%) ^URAM ^BUFG* ^MMCM ^PLL |
| 49014 (20.39%) |69194 (14.39%)|35 (1.82%)| 81 (13.42%) | 0   | 0    | 2   | 5  | 
</WRAP>

==== fmcomms2_vc707 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD            ^DSP48      ^RAMB/FIFO    ^URAM ^BUFG* ^MMCM ^PLL |
| 47637 (15.69%) | 57891 (9.53%)| 32 (1.14%)| 152 (14.76%)| 0   | 14   | 3  | 1  |  
</WRAP>

==== fmcomms2_zc702 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48       ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 13978 (26.17%) | 22537 (21.18%)| 37 (10.55%)| 6 (4.29%)| 0   | 7    | 2   | 0  |
</WRAP>

==== fmcomms2_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48      ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 13927 (6.37%) | 22401 (5.12%)| 37 (4.11%)| 6 (1.1%) | 0   | 7    | 2  | 0 | 
</WRAP>

==== fmcomms2_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD            ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 11189 (4.08%) |19130 (3.49%)| 28 (1.11%)| 4 (0.44%)| 0   | 0    | 0   |  0 |  
</WRAP>

==== fmcomms2_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48      ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 10037 (57%.03)|14700 (41.76%) | 30 (37.5%)| 17 (28.33%)| 0   | 5    | 0   | 0  |
</WRAP>

==== fmcomms5_zc702 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD            ^DSP48       ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 22671 (42.61%) | 37768 (35.5%)| 65 (29.55%)|10 (7.14%) | 0   | 7    | 2   | 0  |
</WRAP>

==== fmcomms5_zc706 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48       ^RAMB/FIFO   ^URAM ^BUFG* ^MMCM ^PLL |
| 22576 (10.33%) | 37424 (8.56%) | 65 (7.22%) | 10 (1.83%) | 0   | 7    | 2   | 0  |
</WRAP>

==== fmcomms5_zcu102 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT           ^FD           ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 19706 (7.19%)|34210 (6.24%)|56 (2.22%)| 8 (0.88%)| 0   | 0   | 0    | 0  |   
</WRAP>

==== imageon_zed ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD(%)        ^DSP48     ^RAMB/FIFO ^URAM ^BUFG* ^MMCM ^PLL |
| 6571 (12.35%) | 8754 (8.23%)|17 (7.73%)| 3 (2.14%)| 0   | 6    | 2   | 0  |
</WRAP>

==== m2k ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD             ^DSP48      ^RAMB/FIFO   ^URAM  ^BUFG* ^MMCM ^PLL |
| 10037 (57.03%) | 14700 (41.76%)| 30 (37.5%)|17 (28.33%) | 0    | 5    | 0   | 0  |
</WRAP> 



==== pluto ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD              ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 7817 (44.41%) | 14142 (40.18%) | 56 (70%) | 2 (3.33%) | 0   | 3    | 0   | 0  |
</WRAP>

==== sidekiqz2 ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT            ^FD             ^DSP48     ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 7817 (44.41%) |14142 (40.12%) | 56 (70%) | 2 (3.33%) | 0   | 3    | 0 |  0   |
</WRAP>

==== usrp31x ====
<WRAP round>
|< 98% 14% 14% 14% 14% 14% 14% 14%>|
^LUT             ^FD              ^DSP48        ^RAMB/FIFO  ^URAM ^BUFG* ^MMCM ^PLL |
| 11420 (21.47%) | 18814 (17.68%) | 28 (12.73%) | 2 (1.43%) | 0   | 3    | 0   | 0  |
</WRAP>

~~NOTOC~~
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