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resources:fpga:docs:hdl:porting_project_quick_start_guide [09 Jan 2018 10:32] – Fix a few grammar mistakes and add a tip related to Xilinx boards Istvan Csomortani | resources:fpga:docs:hdl:porting_project_quick_start_guide [05 Feb 2018 10:14] – Add standalone project porting description Adrian Costina | ||
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====== Porting ADI's HDL reference designs ====== | ====== Porting ADI's HDL reference designs ====== | ||
- | In general, a given reference design | + | In general, a given reference design |
All the HDL projects were designed to maximize source code reuse, minimize maintainability and simplify portability. The result of these design goals is that porting a given project to another carrier is fairly simple if the user respects a couple of guidelines. The main scope of this wiki page is to discuss these guidelines and provide simple indications for users who wants to port a project to a non-supported carrier. | All the HDL projects were designed to maximize source code reuse, minimize maintainability and simplify portability. The result of these design goals is that porting a given project to another carrier is fairly simple if the user respects a couple of guidelines. The main scope of this wiki page is to discuss these guidelines and provide simple indications for users who wants to port a project to a non-supported carrier. | ||
===== Quick Compatibility Check ===== | ===== Quick Compatibility Check ===== | ||
- | < | + | < |
- | there will be no obstacles, which prevents | + | |
- | There is two type of FMC connector: LPC (Low Pin Count) and HPC (High Pin Count). In general, an FMC board is using the FMC connector type, which has enough pins for the required interfaces between the IO devices and FPGA. A carrier with an FMC HPC connector can host FMC board with an LPC or HPC connector, but a carrier with an FMC LPC can host a board just with an FMC LPC connector. | + | There are two types of FMC connector: LPC (Low Pin Count) and HPC (High Pin Count). In general, an FMC board is using the FMC connector type that has enough pins for the required interfaces between the IO devices and FPGA. A carrier with an FMC HPC connector can host FMC boards |
- | <note tip> | + | <note tip> |
- | The most important things to check before porting, are related to the ANSI/VITA 57.1 standard (the list is not necessarily exhaustive): | + | The most important things to check before porting are related to the ANSI/VITA 57.1 standard (the list is not necessarily exhaustive): |
* Power and ground lines - 3P3V/ | * Power and ground lines - 3P3V/ | ||
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* Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N]) | * Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N]) | ||
- | <note important> | + | <note important> |
- | <note tip>Make sure, that you've reviewed all the documentation and design files in order to know the electrical specifications and/or requirements of the FMC board. If you're not sure, ask!</ | + | <note tip>Make sure that you've reviewed all the documentation and design files in order to know the electrical specifications and/or requirements of the FMC board. If you're not sure, ask!</ |
===== Base design files ===== | ===== Base design files ===== | ||
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The **zcu102** directory must contain the following files: | The **zcu102** directory must contain the following files: | ||
- | * **zcu102_system_bd.tcl** - This script | + | * **zcu102_system_bd.tcl** - This script |
- | * **zcu102_system_constr.xdc** - IO constraint file for the base design. Will contain IO definitions for GPIO, switches, LEDs or other peripherals of the board. | + | * **zcu102_system_constr.xdc** - IO constraint file for the base design. Will contain IO definitions for GPIO, switches, LEDs or other peripherals of the board |
* MIG configuration file (if needed) - This file can be borrowed for the golden reference design of the board | * MIG configuration file (if needed) - This file can be borrowed for the golden reference design of the board | ||
* other constraints files if needed | * other constraints files if needed | ||
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==== Example with an Intel board ==== | ==== Example with an Intel board ==== | ||
- | To create a new base design for a given Intel FPGA carrier board, the following steps should be taken (the zcu102 | + | To create a new base design for a given Intel FPGA carrier board the following steps should be taken (the a10soc |
The following files should be created or copied into the directory: | The following files should be created or copied into the directory: | ||
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===== Project files for Xilinx boards ===== | ===== Project files for Xilinx boards ===== | ||
- | To follow the project framework as much as possible, the easiest way is to copy all the projects | + | To follow the project framework as much as possible the easiest way is to copy all the projects |
- | * **system_project.tcl** - This script is creating the actual Vivado project and run the synthesis/ | + | * **system_project.tcl** - This script is creating the actual Vivado project and runs the synthesis/ |
* **system_bd.tcl** - In this file is sourced the base design' | * **system_bd.tcl** - In this file is sourced the base design' | ||
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* **system_constr.xdc** - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names. | * **system_constr.xdc** - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names. | ||
| | ||
- | * **system_top.v** - Top wrapper file, in which the system_wrapper.v module is instantiated, | + | * **system_top.v** - Top wrapper file, in which the system_wrapper.v module is instantiated, |
* **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue. | * **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue. | ||
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===== Project files for Intel boards ===== | ===== Project files for Intel boards ===== | ||
- | To follow the project framework as much as possible, the easiest way is to copy all the projects file from an already existing project and modifying those file to support the new carrier. A project for an Intel FPGA board should contain the following files: | + | To follow the project framework as much as possible the easiest way is to copy all the projects file from an already existing project and modifying those files to support the new carrier. A project for an Intel FPGA board should contain the following files: |
* **system_project.tcl** - This script is creating the actual Quartus project and run the synthesis/ | * **system_project.tcl** - This script is creating the actual Quartus project and run the synthesis/ | ||
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* **system_qsys.tcl** - In this file is sourced the base design' | * **system_qsys.tcl** - In this file is sourced the base design' | ||
- | * **system_constr.sdc** - Contains clock definitions and other proprieties | + | * **system_constr.sdc** - Contains clock definitions and other path constraints |
- | * **system_top.v** - Top wrapper file of the project. The IO port of this verilog module will be actual IO pads of the FPGA. Need to make sure, that the base design' | + | * **system_top.v** - Top wrapper file of the project. The IO port of this verilog module will be actual IO pads of the FPGA. Need to make sure that the base design' |
- | * **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue. | + | * **Makefile** - This is an auto-generated file, but after updating the carrier name, it should work with the new project without an issue. |
+ | |||
+ | ===== Example with a Xilinx standalone project ===== | ||
+ | |||
+ | In some cases, you want to add project which is not based on any carrier, as everything is on a custom board. We have the / | ||
+ | |||
+ | After that, you must update each of the following files: | ||
+ | |||
+ | * **system_project.tcl** - modify the name of the project and the FPGA device that you use | ||
+ | |||
+ | * **system_bd.tcl** | ||
+ | |||
+ | * **system_top.v** | ||
+ | |||
+ | * **system_constr.xdc** - modify the pin constraints and clocks declarations so that they are matching your schematic | ||
+ | |||
+ | * **Makefile** - if you want to use our make infrastructure, | ||
===== Help and support ===== | ===== Help and support ===== |