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resources:fpga:docs:hdl:porting_project_quick_start_guide [01 Sep 2017 12:56] – Update titles Istvan Csomortani | resources:fpga:docs:hdl:porting_project_quick_start_guide [22 Sep 2022 14:43] – Add reference to templates from hdl Iulia Moldovan | ||
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====== Porting ADI's HDL reference designs ====== | ====== Porting ADI's HDL reference designs ====== | ||
- | In general a given reference design | + | In general, a given reference design |
- | All the HDL projects were designed to maximize source code reuse, minimize maintainability and ease portability. The result of these design goals is that porting a given project to another carrier is fairly simple, if the user respects a couple of guide lines. The main scope of this wiki page is to discuss | + | |
+ | All the HDL projects were designed to maximize source code reuse, minimize maintainability and simplify | ||
+ | |||
+ | The main scope of this wiki page is to discuss | ||
===== Quick Compatibility Check ===== | ===== Quick Compatibility Check ===== | ||
- | < | + | < |
- | there will be no obstacles, which prevents | + | |
- | There are two type of FMC connector | + | There are two types of FMC connectors: LPC (Low Pin Count) and HPC (High Pin Count). In general, an FMC board is using the FMC connector type that has enough pins for the required interfaces between the I/O devices and FPGA. A carrier with an FMC HPC connector can host FMC boards |
- | <note tip> | + | <note tip> |
- | The most important things to check before porting, which are related to the ANSI/VITA 57.1 standard (list is not necessarily exhaustive): | + | The most important things to check before porting are related to the ANSI/VITA 57.1 standard (the list is not necessarily exhaustive): |
* Power and ground lines - 3P3V/ | * Power and ground lines - 3P3V/ | ||
* VADJ - adjustable voltage level power from the carrier, each board has a specific requirement for VADJ | * VADJ - adjustable voltage level power from the carrier, each board has a specific requirement for VADJ | ||
- | * Dedicated pins for clock signals - all the clock dedicated pins should be connected to a clock capable pin of the FPGA (IO pin which is capable to receive and/or transmit a clock signal) | + | * Dedicated pins for clock signals - all the clock dedicated pins should be connected to a clock capable pin of the FPGA (I/O pin which is capable to receive and/or transmit a clock signal) |
* Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N]) | * Dedicated pins for transceiver lines (DPx_[M2C|C2M]_[P|N]) | ||
- | <note important> | + | <note important> |
- | <note tip>Make sure, that you' | + | <note tip>Make sure that you have reviewed all the documentation and design files in order to know the electrical specifications and/or requirements of the FMC board. If you're not sure, ask!</ |
===== Base design files ===== | ===== Base design files ===== | ||
- | At [[https:// | + | At [[/ |
+ | |||
+ | <note tip>In [[repo> | ||
==== Example with a Xilinx board ==== | ==== Example with a Xilinx board ==== | ||
- | To create a new base design for a given Xilinx | + | In this section, we are presenting all the necessary steps to create a base design for the Xilinx |
- | First, you need to create a new directory in ~/ | + | First, you need to create a new directory in //~/ |
< | < | ||
[~/ | [~/ | ||
- | The following files should be created or copied into the directory: | + | The **zcu102** directory must contain the following files: |
- | * **zcu102_system_bd.tcl** - In this script | + | * **zcu102_system_bd.tcl** - This script |
- | * **zcu102_system_constr.xdc** - IO constraint file for the base design. | + | * **zcu102_system_constr.xdc** - I/O constraint file for the base design. |
- | * MIG configuration file (if needed) - this can be borrowed for the golden reference design of the board | + | * MIG configuration file (if needed) - This file can be borrowed for the golden reference design of the board |
* other constraints files if needed | * other constraints files if needed | ||
- | You should define the board and its device in the flow script ([[https:// | + | You should define the board and its device in the project |
<code tcl>if [regexp " | <code tcl>if [regexp " | ||
Line 50: | Line 54: | ||
set sys_zynq 2 | set sys_zynq 2 | ||
}</ | }</ | ||
+ | |||
+ | <note tip>The valid board parts and parts can be retrieved by running the following commands in Tcl console: **get_parts** and **get_board_parts**. Run the commands like **join [get_parts] \n**, so each part name will be listed on a separate line.</ | ||
The **sys_zynq** constant variable should be set in the following way: | The **sys_zynq** constant variable should be set in the following way: | ||
Line 58: | Line 64: | ||
==== Example with an Intel board ==== | ==== Example with an Intel board ==== | ||
- | To create a new base design for a given Intel FPGA carrier board, the following steps should be taken (the zcu102 | + | To create a new base design for a given Intel FPGA carrier board, the following steps should be taken (the A10SoC |
The following files should be created or copied into the directory: | The following files should be created or copied into the directory: | ||
- | * **a10soc_system_assign.tcl** - global and IO assignments of the base design | + | * **a10soc_system_assign.tcl** - global and I/O assignments of the base design |
* **a10soc_system_qsys.tcl** - the QSYS base design | * **a10soc_system_qsys.tcl** - the QSYS base design | ||
- | You should define the board and its device in the flow script ([[https:// | + | You should define the board and its device in the flow script ([[https:// |
<code tcl>if [regexp " | <code tcl>if [regexp " | ||
Line 72: | Line 78: | ||
}</ | }</ | ||
- | ===== Project files for Xilinx boards ===== | + | ===== Project files ===== |
+ | |||
+ | ==== Project files for Xilinx boards | ||
+ | |||
+ | To follow the project framework as much as possible, the easiest way is to copy all the projects files from an already existing project and modifying those files to support the new carrier. A project for a Xilinx FPGA board should contain the following files: | ||
+ | |||
+ | * **system_project.tcl** - This script is creating the actual Vivado project and runs the synthesis/ | ||
+ | |||
+ | * **system_bd.tcl** - In this file is sourced the //base// design' | ||
+ | |||
+ | * **system_constr.xdc** - Constraint file of the board design. Here are defined the FMC I/O pins and board specific clock signals. All the I/O definitions must be updated, with the new pin names. | ||
+ | |||
+ | * **system_top.v** - Top wrapper file, in which the system_wrapper.v module is instantiated, | ||
+ | |||
+ | * **Makefile** - This is an auto-generated file, but after updating the carrier name, should work with the new project without an issue. | ||
+ | |||
+ | ==== Project files for Intel boards ==== | ||
+ | |||
+ | To follow the project framework as much as possible the easiest way is to copy all the projects file from an already existing project and modifying those files to support the new carrier. A project for an Intel FPGA board should contain the following files: | ||
+ | |||
+ | * **system_project.tcl** - This script is creating the actual Quartus project and runs the synthesis/ | ||
+ | |||
+ | * **system_qsys.tcl** - In this file is sourced the //base// design' | ||
+ | |||
+ | * **system_constr.sdc** - Contains clock definitions and other path constraints | ||
+ | |||
+ | * **system_top.v** - Top wrapper file of the project. The I/O ports of this Verilog module will be actual I/O pads of the FPGA. You must make sure that the base design' | ||
+ | |||
+ | * **Makefile** - This is an auto-generated file, but after updating the carrier name, it should work with the new project without an issue. | ||
+ | |||
+ | ===== Tips ===== | ||
- | To follow | + | ==== Generating |
- | * **system_project.tcl** - This script is creating | + | The easiest way of writing |
- | * **system_bd.tcl** - In this file is sourced the base design' | + | Required setup: |
- | * **system_constr.xdc** - Constraint files of the board design. Here is defined the FMC IO's and board specific clock signals. All the IO definition must be updated, with the new pin names. | + | * Carrier common FMC connections file ([[repo> |
+ | | ||
- | * **system_top.v** - Top wrapper file of the project. The IO port of this verilog module will be actual IO pads of the FPGA. Need to make sure, that the base design's IOs are updated. (Delete nonexistent IO, or add new ones.) The simplest way to update the system_top is to let the synthesis fail, and the tool will tell which ports are missing or which ports are redundant. | + | <note tip>In cases where these files don't already exist, you can make your own by following some existing |
- | * **Makefile** - This is an auto generated file, but after updating | + | Calling |
- | ===== Project files for Intel boards ===== | + | To use this script you can source it in any tcl shell or simply call the adi_fmc_constr_generator.tcl with argument(s) < |
- | To follow | + | For example: |
+ | * **tclsh ../ | ||
+ | * **tclsh | ||
- | * **system_project.tcl** - This script is creating the actual Quartus project and run the synthesis/ | + | If sourced without argument(s) then you can simply call gen_fmc_constr < |
- | | + | For example: |
+ | | ||
+ | * **gen_fmc_constr fmc0 fmc1** (the project uses two FMC ports at a time) | ||
+ | < | ||
- | | + | The generated file will appear in the current directory as **fmc_constr.xdc** (Xilinx board) or **fmc_constr.tcl** (Intel board). If ran from an open Vivado project, the generated file will be automatically added to the project. |
- | * **system_top.v** - Top wrapper file of the project. The IO port of this verilog module will be actual IO pads of the FPGA. Need to make sure, that the base design' | + | ===== Help and support ===== |
- | * **Makefile** - This is an auto generated file, but after updating the carrier name, should work with the new project without an issue. | + | You can ask questions at [[ez> |
- | ===== Support questions and answers on porting projects ===== | + | Threads that discuss this issue: |
* AD9434 to MicroZed - https:// | * AD9434 to MicroZed - https:// |