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resources:fpga:docs:hdl:fmcomms2_fir_filt [03 Jan 2018 11:22] – Fix a few grammar mistakes and typos Istvan Csomortaniresources:fpga:docs:hdl:fmcomms2_fir_filt [14 Jan 2021 05:24] (current) – use / interwiki links Robin Getz
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 <note important> <note important>
 This example was build using  This example was build using 
-[[ https://github.com/analogdevicesinc/hdl/tree/fmcomms2_fir_filters|fmcomms2_fir_filters ]] GitHub HDL branch, using Vivado 16.2 and 16.4 versions.+[[ https://github.com/analogdevicesinc/hdl/releases/tag/eg_fmcomms2_fir_filter|fmcomms2_fir_filters ]] GitHub HDL branch, using Vivado 16.2 and 16.4 versions.
 </note> </note>
  
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 The same approach is implemented on the receive path. The same approach is implemented on the receive path.
 For more information about the reference design visit: For more information about the reference design visit:
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz |fmcomms2 user guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl| HDL user guide]]+  * [[/resources/fpga/docs/hdl| HDL user guide]]
  
 The modified reference design block diagram containing now Interpolation and Decimation filters is presented below. The modified reference design block diagram containing now Interpolation and Decimation filters is presented below.
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 ==== Adding FIR filters in fmcomms2 design and building the HDL ==== ==== Adding FIR filters in fmcomms2 design and building the HDL ====
  
-In order to use the ADI framework, one needs to set an environment variable pointing to the ADI HDL folder and source the TCL procedures. +The design is obtain by simply sourcing the base fmcomms2 block design.
-<code php> +
-set ad_hdl_dir $::env(ADI_HDL_DIR) +
-set ad_phdl_dir $ad_hdl_dir  +
- +
-source $ad_hdl_dir/projects/scripts/adi_board.tcl +
-source $ad_hdl_dir/projects/scripts/adi_project.tcl +
-</code> +
-  +
-Then we set the “zynq” flag and create the new project. Set the board part property of the current project. (We are using the ZC706 development board in this example)+
  
 <code php> <code php>
-set sys_zynq 1 +set project_dir [pwd] 
-create_project zc706 . -part xc7z045ffg900-2 -force +cd $ad_hdl_dir/projects/fmcomms2/zc706/ 
-set_property board_part xilinx.com:zc706:part0:1.2 [current_project]+source system_bd.tcl 
 +cd $project_dir
 </code> </code>
  
-The board design is created by simply sourcing the carrier's (zc706) board design and the board's board design (fmcomms2). 
- 
-<code php> 
-create_bd_design "system" 
-source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl 
-source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl 
-</code> 
 At this point fmcomms2 reference design's TX data path has the following components: At this point fmcomms2 reference design's TX data path has the following components:
  
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 {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}} {{ :resources:fpga:docs:hdl:ad9361_dma_data.png?nolink |}}
  
-More information about the util_upack_core [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]]+More information about the util_upack_core [[/resources/fpga/docs/util_upack |util_upack_core]]
  
 As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below. As a fact the data transmuted/received trough LVDS interface at DDR (Double Data Rate) is presented in the diagram below.
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 ad_connect fir_decimator_1/decimate decim_slice/Dout ad_connect fir_decimator_1/decimate decim_slice/Dout
 </code> </code>
 +
 +==== Generating the programing files ====
 +
 +Depending if you did your changes in GUI, you can click on "Generate Bitstream". After the bitstream generation is complete. Click on Files > Export > Export Hardware, select include bitstream option.
 +
 +If you did your changes directly in the Tcl files, you can use "make" to generate the bitstream and hdf file.
 +
 +Now depending if your system is based on a zynq architecture, you will have to generate the BOOT.BIN. If you have a MicroBlaze soft processor in your system booting the Linux will is simpler.
 +
 +More info on:
 +  * [[/resources/fpga/docs/build | Building the ADI HDL]]
 +  * [[/resources/tools-software/linux-drivers-all | Building the ADI Linux]]
 +
  
 ==== Base system functionality ==== ==== Base system functionality ====
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   * {{:resources:fpga:docs:hdl:boot.zip|}}   * {{:resources:fpga:docs:hdl:boot.zip|}}
-  * https://github.com/analogdevicesinc/hdl/tree/fmcomms2_fir_filters+  * https://github.com/analogdevicesinc/hdl/releases/tag/eg_fmcomms2_fir_filter
  
 ===== References  ===== ===== References  =====
  
   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html   * https://uk.mathworks.com/help/dsp/ref/fdesign.interpolator.html
-  * [[https://wiki.analog.com/resources/fpga/docs/axi_ad9361|axi_ad9361]] +  * [[/resources/fpga/docs/axi_ad9361|axi_ad9361]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] +  * [[/resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] 
-  * [[https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] +  * [[/resources/eval/user-guides/ad-fmcomms2-ebz|AD-FMCOMMS2-EBZ User Guide]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_upack |util_upack_core]] +  * [[/resources/fpga/docs/util_upack |util_upack_core]] 
-  * [[https://wiki.analog.com/resources/fpga/docs/util_pack |util_pack_core]]+  * [[/resources/fpga/docs/util_cpack |util_pack_core]]
  
  
resources/fpga/docs/hdl/fmcomms2_fir_filt.txt · Last modified: 14 Jan 2021 05:24 by Robin Getz

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