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| resources:fpga:docs:data_offload [09 Nov 2021 09:43] – [Synthesis Configuration Parameters] Nagy Mihaita | resources:fpga:docs:data_offload [11 Aug 2022 11:54] – [Synthesis Configuration Parameters] Laszlo Nagy |
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| ===== Features ===== | ===== Features ===== |
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| * Configurable storage unit with support for Block-RAM and External DRAM (Up to 16 GiB) | * Configurable storage unit with support for Block-RAM and External DRAM (Up to 16 GiB) or external High Bandwidth Memory (HBM) |
| * Configurable interface width and rates | * Configurable interface width and rates |
| * External timing synchronization for precisely timed buffers (For example in combination with the [[resources:fpga:docs:axi_tdd|Timing-Division Duplexing Controller]]) | * External timing synchronization for precisely timed buffers (For example in combination with the [[resources:fpga:docs:axi_tdd|Timing-Division Duplexing Controller]]) |
| | ''ID'' | Instance identification number. | 0 | | | ''ID'' | Instance identification number. | 0 | |
| | ''MEM_TYPE'' | Define the used storage type: 0: BlockRAM; 1: external DDR | 0 | | | ''MEM_TYPE'' | Define the used storage type: 0: BlockRAM; 1: external DDR | 0 | |
| | ''MEM_SIZE'' | Define the size of the storage element in bytes | 1024 | | | ''MEM_SIZE_LOG2'' | Define the log2 size of the storage element in bytes | 10 | |
| | ''MEMC_UIF_DATA_WIDTH'' | The valid data depends on the DDRx memory controller IP. | 512 | | |
| | ''TX_OR_RXN_PATH'' | If set TX path enabled, otherwise RX | 1 | | | ''TX_OR_RXN_PATH'' | If set TX path enabled, otherwise RX | 1 | |
| | ''SRC_DATA_WIDTH'' | The data width of the source interface | 64 | | | ''SRC_DATA_WIDTH'' | The data width of the source interface | 64 | |
| | ''SRC_RAW_DATA_EN'' | Enable if the data path does extend samples to 16 bits | 0 | | |
| | ''SRC_ADDR_WIDTH'' | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/SRC_DATA_WIDTH/8) | 8 | | |
| | ''DST_ADDR_WIDTH'' | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/DST_DATA_WIDTH/8) | 7 | | |
| | ''DST_DATA_WIDTH'' | The data width of the destination interface | 64 | | | ''DST_DATA_WIDTH'' | The data width of the destination interface | 64 | |
| | ''DST_RAW_DATA_EN'' | Enable if the data path does extend samples to 16 bits | 0 | | |
| | ''DST_CYCLIC_EN'' | Enables CYCLIC mode for destinations like DAC | 0 | | | ''DST_CYCLIC_EN'' | Enables CYCLIC mode for destinations like DAC | 0 | |
| | ''AUTO_BRINUP'' | If enabled the IP runs automatically after bootup | 0 | | | ''AUTO_BRINUP'' | If enabled the IP runs automatically after bootup | 0 | |
| | | ''SYNC_EXT_ADD_INTERNAL_CDC '' | If enabled the CDC circuitry for the external sync signal is added | 0 | |
| | | ''HAS_BYPASS '' | If enabled the bypass circuitry is added | 0 | |
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| ===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== |
