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| resources:fpga:docs:build [16 Nov 2021 13:20] – Fix cd command for checking the disk drive Monica Ignat | resources:fpga:docs:build [10 Jan 2022 14:30] – Stefan-Robert Raus |
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| You may now use this 'hdf' file as the input to your no-OS and/or Linux build. | You may now use this 'hdf' file as the input to your no-OS and/or Linux build. Starting with Vivado 2019.3, output file extension got change from .hdf to .xsa. |
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| ====== Tools, Tool versions and Environment ====== | ====== Tools, Tool versions and Environment ====== |
| |Building the project | Source the system_project.tcl file. || | |Building the project | Source the system_project.tcl file. || |
| |Timing Analysis | The projects are usually tested and should be free of timing errors. There is no straightforward method to verify a timing pass (it usually involves writing a TCL proc by itself) on both the tools. The make build will fail and return with an error if the timing is not met (on both tools). || | |Timing Analysis | The projects are usually tested and should be free of timing errors. There is no straightforward method to verify a timing pass (it usually involves writing a TCL proc by itself) on both the tools. The make build will fail and return with an error if the timing is not met (on both tools). || |
| | SDK (Microblaze/Nios) | Use SOPCINFO and SOF files. | Use HDF file.| | | SDK (Microblaze/Nios) | Use SOPCINFO and SOF files. | Use XSA file.| |
| | SDK (ARM/FPGA combo) | <fc #FF0000>Not so well-thought procedure. Need to run different tools, manually edit build files etc. The steps involved are running bsp-editor, running make, modifying linker scripts, makefiles and sources, importing to SDK.</fc> | <fc #008000>Same procedure as Microblaze.</fc> | | | SDK (ARM/FPGA combo) | <fc #FF0000>Not so well-thought procedure. Need to run different tools, manually edit build files etc. The steps involved are running bsp-editor, running make, modifying linker scripts, makefiles and sources, importing to SDK.</fc> | <fc #008000>Same procedure as Microblaze.</fc> | |
| |Upgrading/Version changes (non-ADI cores) |<fc #008000>Quartus automatically updates the cores. Almost hassle-free for most of the cores.</fc> |<fc #FF0000>Vivado does not automatically update the revisions in TCL flow (it does on GUI). It will stop at the first version mismatch (a rather slow and frustrating process).</fc> | | |Upgrading/Version changes (non-ADI cores) |<fc #008000>Quartus automatically updates the cores. Almost hassle-free for most of the cores.</fc> |<fc #FF0000>Vivado does not automatically update the revisions in TCL flow (it does on GUI). It will stop at the first version mismatch (a rather slow and frustrating process).</fc> | |
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| <code> | <code> |
| export PATH=$PATH:/opt/Xilinx/Vivado/2019.1/bin | export PATH=$PATH:/opt/Xilinx/Vivado/202X.X/bin:/opt/Xilinx/Vitis/202X.X/bin |
| export PATH=$PATH:/opt/intelFPGA_pro/19.3/quartus/bin | export PATH=$PATH:/opt/intelFPGA_pro/2X.X/quartus/bin |
| </code> | </code> |
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| <code> | <code> |
| export PATH=$PATH:/cygdrive/d/Xilinx/Vivado/2019.1/bin | export PATH=$PATH:/cygdrive/d/Xilinx/Vivado/202x.x/bin:/cygdrive/d/Xilinx/Vitis/202x.x/bin |
| export PATH=$PATH:/cygdrive/d/intelFPGA_pro/19.3/quartus/bin64 | export PATH=$PATH:/cygdrive/d/intelFPGA_pro/2x.x/quartus/bin64 |
| </code> | </code> |
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| If you do not want to install Cygwin, there may still be some alternatives. There are 'make' alternatives for 'windows command prompt', minimalist GNU for Windows ('MinGW'), or the 'cygwin' variations installed by the tools itself. Some of these may not be fully functional with our scripts and/or projects. If you are an Intel user, the "Nios II Command Shell" do support make. If you are a Xilinx user, use the 'gnuwin' installed as part of the SDK, usually C:\Xilinx\SDK\2019.1\gnuwin\bin. | If you do not want to install Cygwin, there may still be some alternatives. There are 'make' alternatives for 'windows command prompt', minimalist GNU for Windows ('MinGW'), or the 'cygwin' variations installed by the tools itself. Some of these may not be fully functional with our scripts and/or projects. If you are an Intel user, the "Nios II Command Shell" do support make. If you are a Xilinx user, use the 'gnuwin' installed as part of the SDK, usually C:\Xilinx\Vitis\202x.x\gnuwin\bin. |
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| ====== Make: supported targets ====== | ====== Make: supported targets ====== |
| - zynq.bif | - zynq.bif |
| - u-boot.elf | - u-boot.elf |
| - and if you're using ZCU102, then bl31.elf and pmul. | - and if you're using ZCU102, then bl31.elf and pmu.elf |
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| Next, what your project needs, is the **uImage** (or **zImage** for ZCU102) file that you will find in the **zynq-common directory** (or **zynqmp-common** for ZCU102), on your BOOT partition. Copy this file also in the root directory of your project. | Next, what your project needs, is the **uImage**(for zynq based carriers), **Image** (for zynq ultrascale - ZCU102 and adrv9009-zu11eg carriers) or zImage (for Intel based carriers) file that you will find in the **zynq-common / zynqmp-common / socfpga_arria10_common / socfpga_cyclone5_common** on your BOOT partition. Copy this file also in the root directory of your project. |
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| | More info on how to generate this files you will find in the [[resources:fpga:docs:build#References|References]] section or on ReadMe.txt file from boot partition. |
| More info on how to generate this files you will find in the [[resources:fpga:docs:build#References|References]] section. | |
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