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resources:fpga:docs:axi_sysid [14 Nov 2019 12:20] – fixed regmap sergiu arpadiresources:fpga:docs:axi_sysid [13 Oct 2021 10:13] (current) – Edit footer Iulia Moldovan
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 ====== System ID ====== ====== System ID ======
-The System ID solution is comprised of 2 cores: the [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_sysid|axi_sysid]] which provides the AXI Lite interface and [[https://github.com/analogdevicesinc/hdl/tree/master/library/sysid_rom|sysid_rom]] which acts as a ROM and contains the data. Together they provide the user with information regarding the conditions in which the hardware system was built.+The System ID solution is comprised of 2 cores: the [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_sysid|axi_sysid]] which provides the AXI Lite interface and [[https://github.com/analogdevicesinc/hdl/tree/master/library/sysid_rom|sysid_rom]] which acts as a ROM and contains the data. Together they provide the user with information regarding the conditions in which the hardware system was built. \\ 
 +The System ID information is used to provide information about the system’s bit file to facilitate future debugging actions. This information will be stored internally in a ROM and will be made available to the system via the AXI Lite interface. 
 + 
 + 
 +===== Block Diagram =====
  
-==== Block Diagram ==== 
 {{:resources:fpga:docs:sysid1.svg| System ID block diagram}} {{:resources:fpga:docs:sysid1.svg| System ID block diagram}}
    
-====== Introduction ====== 
-The System ID information is used to provide information about the system’s bit file to facilitate future debugging actions. This information will be stored internally in a ROM and will be made available to the system via the AXI Lite interface. 
  
-==== AXI Sysid IP Configuration Parameter ====+===== AXI Sysid IP Configuration Parameters ===== 
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
 | ''ROM_WIDTH'' | ROM width | 32 | | ''ROM_WIDTH'' | ROM width | 32 |
 | ''ROM_ADDR_BITS'' | Number of address bits| 9 | | ''ROM_ADDR_BITS'' | Number of address bits| 9 |
  
-==== AXI Sysid IP Signal and Interface Pins ====+===== AXI Sysid IP Signal and Interface Pins ===== 
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
 |              | ''sys_rom_data'' | ''input'' | Data input from System ROM | |              | ''sys_rom_data'' | ''input'' | Data input from System ROM |
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 |              | ''s_axi_aresetn'' | ''input'' | AXI reset | |              | ''s_axi_aresetn'' | ''input'' | AXI reset |
  
-==== Sysid ROM IP Configuration Parameter ====+===== Sysid ROM IP Configuration Parameters ===== 
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
 | ''ROM_WIDTH'' | ROM width | 32 | | ''ROM_WIDTH'' | ROM width | 32 |
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 | ''PATH_TO_FILE'' | Location of ROM init file | "path_to_mem_init_file" | | ''PATH_TO_FILE'' | Location of ROM init file | "path_to_mem_init_file" |
  
-==== Sysid ROM IP Signal and Interface Pins ====+===== Sysid ROM IP Signal and Interface Pins ===== 
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
 |              | ''clk'' | ''input'' | Input clock | |              | ''clk'' | ''input'' | Input clock |
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 |              | ''rom_data'' | ''output'' | Data output| |              | ''rom_data'' | ''output'' | Data output|
  
-==== Register Map ====        + 
 +===== Register Map =====       
 +  
 {{page>:resources:fpga:docs:hdl:regmap##System ID (axi_system_id)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##System ID (axi_system_id)&nofooter&noeditbtn}}
  
  
-==== Clocking ====+===== Clocking ===== 
 The IP core runs on the AXI clock and requires a frequency of 100MHz. The IP core runs on the AXI clock and requires a frequency of 100MHz.
  
-==== Theory of Operation ====+ 
 +===== Theory of Operation =====
  
 The System ID consists of a system of 2 or more IP cores where one provides access to the AXI Lite interface, and the other behaves as a ROM. There can be more than one ROM IP cores if required. The information contained by the ROM will be generated and written at synthesis and will provide details as revealed further in this document.  The System ID consists of a system of 2 or more IP cores where one provides access to the AXI Lite interface, and the other behaves as a ROM. There can be more than one ROM IP cores if required. The information contained by the ROM will be generated and written at synthesis and will provide details as revealed further in this document. 
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 Once written, these contents cannot be changed, only read. These ROMs will be 32 bits wide with a fixed length of 512 lines for the System ROM (2KiB). The secondary PR ROM will generally be smaller. Once written, these contents cannot be changed, only read. These ROMs will be 32 bits wide with a fixed length of 512 lines for the System ROM (2KiB). The secondary PR ROM will generally be smaller.
  
-==== Data format ==== 
  
-=== Common Header ===+===== Data format ===== 
 + 
 +==== Common Header ====
  
 ^ Field size ^ Field ^ Value ^ Data format^ ^ Field size ^ Field ^ Value ^ Data format^
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 | 4B *       | Checksum                                  |                                                                 | hex | | 4B *       | Checksum                                  |                                                                 | hex |
  
-=== Internal Use Area ===+==== Internal Use Area ====
  
 ^ Field size ^ Field ^ Data format^ ^ Field size ^ Field ^ Data format^
 +| 28B *      | Git branch                                                  | hex |
 | 44B *      | Git tag (sha)                                               | hex | | 44B *      | Git tag (sha)                                               | hex |
 | 4B *       | Git clean check                                             | hex | | 4B *       | Git clean check                                             | hex |
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 **PR Custom String Area:** This area provides a region where a custom string provided by the user will be written to. This will be stored in ROM2, inside the PR bit where available. Data converted from ASCII to hex. **PR Custom String Area:** This area provides a region where a custom string provided by the user will be written to. This will be stored in ROM2, inside the PR bit where available. Data converted from ASCII to hex.
  
-==== Working with the Core ====+ 
 +===== Working with the Core =====
  
 The System ID solution is automatically placed into a project by the Tcl code ADI uses to build projects. It is instantiated in two stages, first in the "Common" bd.tcl of each of the supported FPGA boards and second in the system_bd.tcl of each project. The System ID solution is automatically placed into a project by the Tcl code ADI uses to build projects. It is instantiated in two stages, first in the "Common" bd.tcl of each of the supported FPGA boards and second in the system_bd.tcl of each project.
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 sysid_gen_sys_init_file $sys_cstring sysid_gen_sys_init_file $sys_cstring
 </code> </code>
 +
 +
 +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_sysid.1573730445.txt.gz · Last modified: 14 Nov 2019 12:20 by sergiu arpadi

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