Differences

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--- resources:fpga:docs:axi_logic_analyzer [06 Jun 2018 12:56] – Reviewed Adrian Costina
+++ resources:fpga:docs:axi_logic_analyzer [10 Jun 2019 21:45] – Instrument trigger update Andrei Grozav
@@ Line 15: / Line 15: @@
 ==== Block Diagram ====
-{{ :resources:fpga:docs:axi_logic_analyzer.svg | AXI_LOGIC_ANALYZER Block diagram }}
+AXI logic analyzer main module:
+{{:resources:fpga:docs:axi_logic_analyzer_diagram.png|}}
+Logic analyzer trigger submodule:
+{{:resources:fpga:docs:axi_logic_analyzer_trigger.png|}}
 ==== Interface ====
@@ Line 59: / Line 63: @@
 ==== Register Map ====
-|< 100% 5% 5% 5% 25% 5% 55% >|
+|< 100% 5% 5% 5% 25% 5% 5% 50% >|
-|Address ||Bits |Name |Type |Description |
+|Address ||Bits |Name |Type |Default |Description |
-|DWORD |BYTE |::: |::: |::: |::: |
+|DWORD |BYTE |::: |::: |::: |::: |::: |
-^0x0000 ^0x0000 ^REG_VERSION ^^^Version Register ^
+^0x0000 ^0x0000 ^REG_VERSION ^^^^Version Register ^
-| | |[31:0] |VERSION |RO |Version number |
+| | |[31:0] |VERSION |RO |0x00 |Version number |
-^0x0001 ^0x0004 ^REG_SCRATCH ^^^Scratch Register ^
+^0x0001 ^0x0004 ^REG_SCRATCH ^^^^Scratch Register ^
-| | |[31:0] |SCRATCH |RW |Scratch register |
+| | |[31:0] |SCRATCH |RW |0x00 |Scratch register |
-^0x0002 ^0x0008 ^REG_DIVIDER_COUNTER_LA ^^^Downsampling Counter ^
+^0x0002 ^0x0008 ^REG_DIVIDER_COUNTER_LA ^^^^Downsampling Counter ^
-| | |[31:0] |DIVIDER_COUNTER |RW |Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples |
+| | |[31:0] |DIVIDER_COUNTER |RW |0x00 |Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples |
-^0x0003 ^0x000c ^REG_DIVIDER_COUNTER_PG ^^^Upsampling Counter  ^
+^0x0003 ^0x000c ^REG_DIVIDER_COUNTER_PG ^^^^Upsampling Counter  ^
-| | |[31:0] |DIVIDER_COUNTER |RW |Register used for upsampling pattern generator data. Sample data every  (divider counter + 1) samples |
+| | |[31:0] |DIVIDER_COUNTER |RW |0x00 |Register used for upsampling pattern generator data. Sample data every  (divider counter + 1) samples |
-^0x0004 ^0x0010 ^REG_IO_SELECTION ^^^Data Pins Direction ^
+^0x0004 ^0x0010 ^REG_IO_SELECTION ^^^^Data Pins Direction ^
-| | |[15:0] |DIRECTION |RW |Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin |
+| | |[15:0] |DIRECTION |RW |0x00 |Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin |
-^0x0005 ^0x0014 ^REG_EDGE_DETECT_CONTROL ^^^Any Edge Triggering ^
+^0x0005 ^0x0014 ^REG_EDGE_DETECT_CONTROL ^^^^Any Edge Triggering ^
-| | |[17:16] |TRIGGER[1:0] |RW |Enables any edge detection triggering based on the trigger pins |
+| | |[17:16] |TRIGGER[1:0] |RW |0x00 |Enables any edge detection triggering based on the trigger pins |
-|::: |::: |[15:0] |DATA |RW |Enables any edge detection triggering based on the data pins |
+|::: |::: |[15:0] |DATA |RW |0x00 |Enables any edge detection triggering based on the data pins |
-^0x0006 ^0x0018 ^REG_RISE_EDGE_CONTROL ^^^Rise Edge Triggering ^
+^0x0006 ^0x0018 ^REG_RISE_EDGE_CONTROL ^^^^Rise Edge Triggering ^
-| | |[17:16] |TRIGGER[1:0] |RW |Enables rise edge detection triggering based on the trigger pins |
+| | |[17:16] |TRIGGER[1:0] |RW |0x00 |Enables rise edge detection triggering based on the trigger pins |
-|::: |::: |[15:0] |DATA[15:0] |RW |Enables rise edge detection triggering based on the data pins |
+|::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables rise edge detection triggering based on the data pins |
-^0x0007 ^0x001c ^REG_FALL_EDGE_CONTROL ^^^Fall Edge Triggering ^
+^0x0007 ^0x001c ^REG_FALL_EDGE_CONTROL ^^^^Fall Edge Triggering ^
-| | |[17:16] |TRIGGER[1:0] |RW |Enables fall edge detection triggering based on the trigger pins |
+| | |[17:16] |TRIGGER[1:0] |RW |0x00 |Enables fall edge detection triggering based on the trigger pins |
-|::: |::: |[15:0] |DATA[15:0] |RW |Enables fall edge detection triggering based on the data pins |
+|::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables fall edge detection triggering based on the data pins |
-^0x0008 ^0x0020 ^REG_LOW_LEVEL_CONTROL ^^^Low Level Triggering ^
+^0x0008 ^0x0020 ^REG_LOW_LEVEL_CONTROL ^^^^Low Level Triggering ^
-| | |[17:16] |TRIGGER[1:0] |RW |Enables low level triggering based on the trigger pins |
+| | |[17:16] |TRIGGER[1:0] |RW |0x00 |Enables low level triggering based on the trigger pins |
-|::: |::: |[15:0] |DATA[15:0] |RW |Enables low level triggering based on the data pins |
+|::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables low level triggering based on the data pins |
-^0x0009 ^0x0024 ^REG_HIGH_LEVEL_CONTROL ^^^High Level Triggering ^
+^0x0009 ^0x0024 ^REG_HIGH_LEVEL_CONTROL ^^^^High Level Triggering ^
-| | |[17:16] |TRIGGER[1:0] |RW |Enables high level triggering based on the trigger pins |
+| | |[17:16] |TRIGGER[1:0] |RW |0x00 |Enables high level triggering based on the trigger pins |
-|::: |::: |[15:0] |DATA[15:0] |RW |Enables high level triggering based on the data pins |
+|::: |::: |[15:0] |DATA[15:0] |RW |0x00 |Enables high level triggering based on the data pins |
-^0x000A ^0x0028 ^REG_FIFO_DEPTH ^^^Controls the Dynamic Depth of the History FIFO ^
+^0x000A ^0x0028 ^REG_FIFO_DEPTH ^^^^Controls the Dynamic Depth of the History FIFO ^
-| | |[31:0] |FIFO_DEPTH |RW |Controls the depth of the history FIFO. Should be less than the maximum FIFO depth.  If set to 0, the FIFO is bypassed and reset |
+| | |[31:0] |FIFO_DEPTH |RW |0x00 |Controls the depth of the history FIFO. Should be less than the maximum FIFO depth.  If set to 0, the FIFO is bypassed and reset |
-^0x000B ^0x002c ^REG_TRIGGER_LOGIC ^^^Trigger Mix ^
+^0x000B ^0x002c ^REG_TRIGGER_LOGIC ^^^^Trigger Mix ^
-| | |[0] |TRIGGER_LOGIC |RW |Combines the enable triggers through an OR (0) or an AND (1) gate |
+| | |[6:4] |TRIGGER_MUX_OUT |RW |0x00 |Final Trigger Selection Multiplexer \\ Selects triggers: \\   0: TRIGGER_LOGIC \\   1: ADC TRIGGER \\   2: TRIGGER_LOGIC AND ADC TRIGGER \\   3: TRIGGER_LOGIC OR  ADC TRIGGER \\   4: TRIGGER_LOGIC XOR ADC TRIGGER |
-^0x000C ^0x0030 ^REG_CLOCK_SELECT ^^^Clock Selection Multiplexer ^
+|::: |::: |[0] |TRIGGER_LOGIC |RW |0x00 |Combines the enable triggers through an OR (0) or an AND (1) gate |
-| | |[0] |CLOCK_SELECT |RW |Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths |
+^0x000C ^0x0030 ^REG_CLOCK_SELECT ^^^^Clock Selection Multiplexer ^
-^0x000D ^0x0034 ^REG_OVERWRITE_MASK ^^^Overwrite data_o Value ^
+| | |[0] |CLOCK_SELECT |RW |0x00 |Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths |
-| | |[15:0] |OVERWRITE_MASK |RW |If set to 1, the specific data_o pin will be driven by the value written in the  REG_OVERWRITE_DATA register, instead of the DMA |
+^0x000D ^0x0034 ^REG_OVERWRITE_MASK ^^^^Overwrite data_o Value ^
-^0x000E ^0x0038 ^REG_OVERWRITE_DATA ^^^Overwrite Value for data_o ^
+| | |[15:0] |OVERWRITE_MASK |RW |0x00 |If set to 1, the specific data_o pin will be driven by the value written in the  REG_OVERWRITE_DATA register, instead of the DMA |
-| | |[15:0] |OVERWRITE_DATA |RW  |Overwrite value to drive data_o directly, when the mask is applied |
+^0x000E ^0x0038 ^REG_OVERWRITE_DATA ^^^^Overwrite Value for data_o ^
-^0x000F ^0x003c ^REG_INPUT_DATA ^^^Read the Value on data_i Bus ^
+| | |[15:0] |OVERWRITE_DATA |RW  |0x00 |Overwrite value to drive data_o directly, when the mask is applied |
-| | |[15:0] |INPUT_DATA |RO |The value of the input data, synchronized |
+^0x000F ^0x003c ^REG_INPUT_DATA ^^^^Read the Value on data_i Bus ^
-^0x0010 ^0x0040 ^REG_OUTPUT_MODE ^^^Controls Output Type ^
+| | |[15:0] |INPUT_DATA |RO |0x00 |The value of the input data, synchronized |
-| | |[15:0] |OUTPUT_MODE |RW |Data output is in push-pull (0) or open-drain(1) mode |
+^0x0010 ^0x0040 ^REG_OUTPUT_MODE ^^^^Controls Output Type ^
-^0x0011 ^0x0044 ^REG_TRIGGER_DELAY ^^^Control the Trigger Delay ^
+| | |[0] |OUTPUT_MODE |RW |0x00 |Data output is in push-pull (0) or open-drain(1) mode |
-| | |[31:0] |TRIGGER_DELAY |RW |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger |
+^0x0011 ^0x0044 ^REG_TRIGGER_DELAY ^^^^Control the Trigger Delay ^
-^0x0012 ^0x0048 ^REG_TRIGGERED ^^^Indicates Triggering Status ^
+| | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger |
-| | |[0] |TRIGGERED |RW1C |Indicates if the trigger has been triggered since the last time this register has been reset. |
+^0x0012 ^0x0048 ^REG_TRIGGERED ^^^^Indicates Triggering Status ^
-^0x0013 ^0x004c ^REG_STREAMING ^^^Controls Streaming Mode ^
+| | |[0] |TRIGGERED |RW1C |0x00 |Indicates if the trigger has been triggered since the last time this register has been reset. |
-| | |[0] |STREAMING |RW |If the streaming bit is set, after the trigger condition is met data will be continuosly  captured by the DMA. The streaming bit must be set to 0 to reset triggering.  |
+^0x0013 ^0x004c ^REG_STREAMING ^^^^Controls Streaming Mode ^
+| | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuosly  captured by the DMA. The streaming bit must be set to 0 to reset triggering.  |
+^Mon Jun 10 13:44:24 2019 ^^^^^^
 ==== References ====

Wiki

Analog Devices Wiki

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