AXI Laser Driver IP core

The axi_laser_driver IP generate all the necessary control signal for the ad_fmclidar1_ebz prototyping platform, to drive the laser, switch between the TIA channels and synchronize all the data flow inside the FPGA. This documentation covers the main functionality of the IP core and its software programmable registers.

Features

PWM generator with a free running counter
Software configurable frequency and pulse width for the PWM
Control and status lines for the ADP3624 MOSFET driver
Software configurable interrupts
Software configurable TIA channel sequencer

Block Diagram

Parameters

Name	Description	Default Value
`ID`	Core ID should be unique for each instance of the IP	0
`ASYNC_CLK_EN`	Bit must be set if the core clock is different from the AXI Memory Mapped interface clock	1
`PULSE_WIDTH`	The pulse width of the generated signal. The resolution is the core clock's time period.	7
`PULSE_PERIOD`	The period of the generated signal. The resolution is the core clock's time period.	1000

I/O interface

Interface	Pin	Type	Description
AXI_S_MM interface
	`s_axi_*`		Standard AXI Slave Memory Map interface
External clock
	`ext_clk`	`input`	An external clock input. If ASYNC_CLK_EN is set, this clock will be used as the core clock.
Laser driver controls and status
	`driver_en_n`	`output`	This line will control the MOSFET driver's shot down pin. If set the MOSFET driver is not working.
	`driver_pulse`	`output`	Generated pulse, which is used to drive the laser
	`driver_otw_n`	`input`	Over temperature warning flag of the MOSFET driver.
	`driver_dp_reset`	`output`	A reset signal, which asserts right before the generated pulse. This signal can be used for preconditioning various IPs of the data path.
	`tia_chsel`	`output[7:0]`	Control lines for the TIA channel multiplexer.

Interrupt
	`irq`	`output`	Interrupt signal

Register Map

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00010061	Version number. Current version is 1.00.a
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_MAGIC				Version and Scratch Registers
		[31:0]	IDENTIFICATION	RO	0x4C534452	Unique identification number of the IP, its value stands for 'LSDR' in ASCII
0x0004	0x0010	REG_CONFIG_PWM				Configuration Registers
		[0]	RESET	RW	0x1	Reset bit of the core. By default the core is in reset.
		[1]	LOAD_CONFIG	RW	0x0	Set this bit to load the configuration of the PWM generator. (width and period)
0x0005	0x0014	REG_CONFIG_PERIOD				Configuration Registers
		[31:0]	PWM_PERIOD	RW	PULSE_PERIOD	The period of the generated signal. The resolution is the core clock's time period. LOAD_CONFIG bit must be asserted to load the registers value into the PWM logic.
0x0006	0x0018	REG_CONFIG_WIDTH				Configuration Registers
		[31:0]	PWM_WIDTH	RW	PULSE_WIDTH	The pulse width of the generated signal. The resolution is the core clock's time period. LOAD_CONFIG bit must be asserted to load the registers value into the PWM logic.
0x0020	0x0080	REG_CONFIG_LDRIVER				Configuration Registers
		[0]	DRIVER_ENABLE_N	RW	0x1	Reset this bit to bring up the MOSFET driver on laser board. By default the laser is disabled.
0x0021	0x0084	REG_STATUS_LDRIVER				Configuration Registers
		[0]	DRIVER_OTW	RO	0x0	The status of the OTW (over temperature warning flag) pin of the MOSFET driver.
0x0022	0x0088	REG_EXT_CLK_MONITOR				Status Registers
		[31:0]	EXT_CLK_FREQ	RO	0x000000000	The core clock's frequency. This clock is used for example by PWM counter too. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz.
0x0028	0x00A0	REG_IRQ_MASK				Interrupt Registers
		[0]	IRQ_PULSE_MASK	RW	0x0	Interrupt mask bit for IRQ_PULSE. By default all interrupt sources are masked out.
		[1]	IRQ_OTW_ENTER_MASK	RW	0x0	Interrupt mask bit for IRQ_OTW_ENTER. By default all interrupt sources are masked out.
		[2]	IRQ_OTW_EXIT_MASK	RW	0x0	Interrupt mask bit for IRQ_OTW_EXIT. By default all interrupt sources are masked out.
0x0029	0x00A4	REG_IRQ_PENDING				Interrupt Registers
		[0]	IRQ_PULSE_PENDING	RW1C	0x0	This bit is set if a pulse was generated, and the IRQ_PULSE_MASK bit is not set. Set this bit after the interrupt was handled as required.
		[1]	IRQ_OTW_ENTER_PENDING	RW1C	0x0	This bit is set if the MOSFET driver enters in OTW state, and the IRQ_OTW_ENTER_MASK bit is not set. Set this bit after the interrupt was handled as required.
		[2]	IRQ_OTW_EXIT_PENDING	RW1C	0x0	This bit is set if the MOSFET driver enters in OTW state, and the IRQ_OTW_EXIT_MASK bit is not set. Set this bit after the interrupt was handled as required.
0x002A	0x00A8	REG_IRQ_SOURCE				Interrupt Registers
		[0]	IRQ_PULSE_SOURCE	RO	0x0	This bit is set if a pulse was generated. Cleared together with the corresponding IRQ_PENDING bit.
		[1]	IRQ_OTW_ENTER_SOURCE	RO	0x0	This bit is set if the MOSFET driver enters in OTW state. Cleared together with the corresponding IRQ_PENDING bit.
		[2]	IRQ_OTW_EXIT_SOURCE	RO	0x0	This bit is set if the MOSFET driver exits in OTW state. Cleared together with the corresponding IRQ_PENDING bit.
0x002B	0x00AC	REG_SEQUENCER_CONTROL				TIA Sequencer Registers
		[0]	SEQUENCER_ENABLE	RW	0x0	Set this bit to enable the TIA channel sequencer.
		[1]	AUTO_SEQUENCE_EN	RW	0x1	If set, the sequencer runs in auto mode, using the predefined sequence. Otherwise the software must set the REG_TIA_MANUAL_CONFIG register to change the TIA channel selection.
0x002C	0x00B0	REG_SEQUENCER_OFFSET				TIA Sequencer Registers
		[31:0]	TIA_CHSEL_OFFSET	RW	0x0	Defines the time between setting the TIA channel select lines and the next generated pulse.
0x002D	0x00B4	REG_SEQUENCE_AUTO_CONFIG				TIA Sequencer Registers
		[1:0]	SEQUENCE_VALUE0	RW	0x0	The value of the TIA channel selects lines in the first sequence.
		[5:4]	SEQUENCE_VALUE1	RW	0x1	The value of the TIA channel selects lines in the second sequence.
		[9:8]	SEQUENCE_VALUE2	RW	0x2	The value of the TIA channel selects lines in the third sequence.
		[13:12]	SEQUENCE_VALUE3	RW	0x3	The value of the TIA channel selects lines in the fourth sequence.
0x002E	0x00B8	REG_TIA_MANUAL_CONFIG				TIA Sequencer Registers
		[1:0]	TIA0_CHSEL_MANUAL	RW	0x0	The value of the TIA0 channel selects lines in manual mode.
		[5:4]	TIA1_CHSEL_MANUAL	RW	0x0	The value of the TIA0 channel selects lines in manual mode.
		[9:8]	TIA2_CHSEL_MANUAL	RW	0x0	The value of the TIA0 channel selects lines in manual mode.
		[13:12]	TIA3_CHSEL_MANUAL	RW	0x0	The value of the TIA0 channel selects lines in manual mode.

Functional description

TBD

Prev.: AXI IPUp: Main pageNext.: Using and modifying the HDL design

Wiki

Analog Devices Wiki

Table of Contents

AXI Laser Driver IP core

Features

Block Diagram

Parameters

I/O interface

Register Map

Functional description

Analog Devices Wiki

Table of Contents

AXI Laser Driver IP core

Features

Block Diagram

Parameters

I/O interface

Register Map

Functional description

Page Tools