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Fan Control IP Core

The axi_fan_control IP core is a software programmable fan controller.

Block Diagram

Introduction

The purpose of this IP core is to control the fan used for the cooling of a Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature sensors. To achieve this, the IP core uses the PL SYSMONE4 primitive to obtain the PL temperature via the DRP interface. Based on the temperature readings it then outputs a PWM signal to control the fan rotation accordingly. The tacho signal coming from the fan is also measured and evaluated to ensure that the RPM is correct and the fan is working properly.

Configuration Parameter

Name	Description	Default Value
`PWM_FREQUENCY_HZ`	Frequency of the PWM signal	5000
`THRESH_PWM_000`	Temperature threshold	0x8f5e (5°C)
`THRESH_PWM_025_L`	Temperature threshold	0x96f0 (20°C)
`THRESH_PWM_025_H`	Temperature threshold	0xa0ff (40°C)
`THRESH_PWM_050_L`	Temperature threshold	0xab03 (60°C)
`THRESH_PWM_050_H`	Temperature threshold	0xb00a (70°C)
`THRESH_PWM_075_L`	Temperature threshold	0xb510 (80°C)
`THRESH_PWM_075_H`	Temperature threshold	0xba17 (90°C)
`THRESH_PWM_100`	Temperature threshold	0xbc9b (95°C)

Signal and Interface Pins

Interface	Pin	Type	Description
	`tacho`	`input`	Tacho generator input
	`pwm`	`output`	PWM control signal
	`irq`	`output`	Interrupt signal, high level
`s_axi`			AXI Slave Memory Map interface
	`s_axi_aclk`	`input`	AXI clock
	`s_axi_aresetn`	`input`	AXI reset

Register Map

Fan Controller (axi_fan_control)

Click to expand regmap

0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x0001
		[15:8]	VERSION_MINOR	RO	0x00
		[7:0]	VERSION_PATCH	RO	0x61
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	`ID`	Value of the ID configuration parameter.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x46414E43	Peripheral identification ('F', 'A', 'N', 'C').
0x10	0x0040	IRQ_MASK
		[3]	NEW_TACHO_MEASUREMENT	RW	0x1	Masks the TACHO_MEASUREMENT_DONE IRQ.
		[2]	TEMP_INCREASE	RW	0x1	Masks the TEMP_INCREASE IRQ.
		[1]	TACHO_ERR	RW	0x1	Masks the TACHO_ERR IRQ.
		[0]	PWM_CHANGED	RW	0x1	Masks the PWM_CHANGED IRQ.
0x11	0x0044	IRQ_PENDING
		[3]	NEW_TACHO_MEASUREMENT	RW1C	0x0	This bit will be asserted when the hardware has written a new value to the TACHO_MEASUREMENT register if the NEW_TACHO_MEASUREMENT bit in the IRQ_MASK register is not set.
		[2]	TEMP_INCREASE	RW1C	0x0	This bit will be asserted whenever the HW decides to increase the PWM duty-cycle, indicating a rise in temperature, and if the TEMP_INCREASE bit in the IRQ_MASK register is not set.
		[1]	TACHO_ERR	RW1C	0x0	This bit will be asserted when a fault related to the tacho signal is detected. This can either mean that the tacho has not toggled in 5 seconds or that the period of the tacho signal is no longer whithin the defined valid interval. Also, the TACHO_ERR bit in the IRQ_MASK register must not be set.
		[0]	PWM_CHANGED	RW1C	0x0	This bit will be asserted when a 5 second delay expires after the PWM width was changed. The delay is used to allow the fan rotation speed to stabilize. Also, the PWM_CHANGED bit in the IRQ_MASK register must not be set.
0x12	0x0048	IRQ_SOURCE
		[3]	NEW_TACHO_MEASUREMENT	RO	0x0	This bit will be asserted when the hardware has written a new value to the TACHO_MEASUREMENT register.
		[2]	TEMP_INCREASE	RO	0x0	This bit will be asserted whenever the hardware decides to increase the PWM duty-cycle indicating a rise in temperature.
		[1]	TACHO_ERR	RO	0x0	This bit will be asserted when a fault related to the tacho signal is detected. This can either mean that the tacho has not toggled in 5 seconds or that the period of the tacho signal is no longer whithin the defined valid interval.
		[0]	PWM_CHANGED	RO	0x0	This bit will be asserted when a 5 second delay expires after the PWM width was changed. The delay is used to allow the fan rotation speed to stabilize.
0x20	0x0080	REG_RSTN
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x21	0x0084	PWM_WIDTH
		[31:0]	PWM_WIDTH	RW	`PWM_PERIOD`	This register contains the width of the PWM output signal. By default its value is established by the hardware after reading the temperature. By writing to this register the software can change the value however this is only possible if the requested value is greater than the value selected by the hardware and not exceeding the PWM period.
0x22	0x0088	TACHO_PERIOD
		[31:0]	TACHO_PERIOD	RW	0x00000000	After using the PWM_WIDTH register to request a different duty-cycle, the software can use this register to define the target period of the tacho signal. This is used together with the TACHO_TOLERANCE register to define an interval for the tacho signal. This register must be written before the TACHO_TOLERANCE register. The hardware will then use this interval to monitor the tacho signal coming from the fan.
0x23	0x008c	TACHO_TOLERANCE
		[31:0]	TACHO_TOLERANCE	RW	0x00000000	This register is used together with the TACHO_PERIOD register to define an interval for the fan's tacho signal. Writing to this register enables the hardware to start monitoring the tacho signal and so it must be written after the TACHO_PERIOD register.
0x24	0x0090	TEMP_DATA_SOURCE
		[31:0]	TEMP_DATA_SOURCE	RO	`INTERNAL_SYSMONE`	This register copies the value from the INTERNAL_SYSMONE register and is used to inform the software what the source of the temperature information is.
0x30	0x00c0	PWM_PERIOD
		[31:0]	PWM_PERIOD	RO	0x4E20	This register contains the period for the PWM output signal. Derived from the PWM_FREQUENCY_HZ parameter.
0x31	0x00c4	TACHO_MEASUREMENT
		[31:0]	TACHO_MEASUREMENT	RO	0x00000000	This register contains the measurement results of the tacho signal period performed by the hardware.
0x32	0x00c8	TEMPERATURE
		[31:0]	TEMPERATURE	RO	0x00000000	This register contains the latest temperature reading from the SYSMONE primitive.
0x40	0x0100	TEMP_00_H
		[31:0]	TEMP_00_H	RW	`TEMP_00_H`	Temperature threshold below which PWM should be 0%
0x41	0x0104	TEMP_25_L
		[31:0]	TEMP_25_L	RW	`TEMP_25_L`	Temperature threshold above which PWM should be 25%
0x42	0x0108	TEMP_25_H
		[31:0]	TEMP_25_H	RW	`TEMP_25_H`	Temperature threshold below which PWM should be 25%
0x43	0x010c	TEMP_50_L
		[31:0]	TEMP_50_L	RW	`TEMP_50_L`	Temperature threshold above which PWM should be 50%
0x44	0x0110	TEMP_50_H
		[31:0]	TEMP_50_H	RW	`TEMP_50_H`	Temperature threshold below which PWM should be 50%
0x45	0x0114	TEMP_75_L
		[31:0]	TEMP_75_L	RW	`TEMP_75_L`	Temperature threshold above which PWM should be 75%
0x46	0x0118	TEMP_75_H
		[31:0]	TEMP_75_H	RW	`TEMP_75_H`	Temperature threshold below which PWM should be 75%
0x47	0x011c	TEMP_100_L
		[31:0]	TEMP_100_L	RW	`TEMP_100_L`	Temperature threshold above which PWM should be 100%
0x50	0x0140	TACHO_25
		[31:0]	TACHO_25	RW	`TACHO_T25`	Nominal tacho period at 25% PWM
0x51	0x0144	TACHO_50
		[31:0]	TACHO_50	RW	`TACHO_T50`	Nominal tacho period at 50% PWM
0x52	0x0148	TACHO_75
		[31:0]	TACHO_75	RW	`TACHO_T75`	Nominal tacho period at 75% PWM
0x53	0x014c	TACHO_100
		[31:0]	TACHO_100	RW	`TACHO_T100`	Nominal tacho period at 100% PWM
0x54	0x0150	TACHO_25_TOL
		[31:0]	TACHO_25_TOL	RW	`TACHO_T25` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 25% PWM tacho period
0x55	0x0154	TACHO_50_TOL
		[31:0]	TACHO_50_TOL	RW	`TACHO_T50` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 50% PWM tacho period
0x56	0x0158	TACHO_75_TOL
		[31:0]	TACHO_75_TOL	RW	`TACHO_T75` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 75% PWM tacho period
0x57	0x015c	TACHO_100_TOL
		[31:0]	TACHO_100_TOL	RW	`TACHO_T100` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 100% PWM tacho period
Tue Mar 14 10:17:59 2023

Clocking

The IP core runs on the AXI clock and requires a frequency of 100MHz.

Theory of Operation

The main features of this IP core are its independent operation and the fact that it does not require an external temperature sensor. All of the mechanisms contained inside the core are controlled by a state machine, so that they do not depend on the software in case the software fails. The state machine uses the temperature it reads from the SYSMONE4 primitive to decide the correct PWM duty-cycle. The temperature thresholds and hysteresis are defined in the hardware and cannot be modified by the software.

Running independently

The hardware can operate with minimal input from the software. Because by default the IP core starts IN-RESET, the software must write 0x1 to the REG_RSTN register to bring up the hardware. In order to activate the interrupts the software must also write to the IRQ_MASK register. At this point the hardware starts operating and a minimal feedback is provided.

There are 9 temperature intervals defined in the hardware as below:

Five of these intervals have only one possible duty-cycle and four of them can have either of the neighbouring values. After reset the PWM duty-cycle will start as 100%. The state-machine will begin reading the temperature from the SYSMONE4 primitive and will decide on the PWM duty cycle depending on which interval the value matches. The PWM duty-cycle will only change when the temperature enters one of the five intervals with a single PWM duty-cycle, in the other four the previous duty-cycle will be maintained. In these intervals its value will depend on whether the temperature is rising or falling. The temperature thresholds can be redefined using the parameters.

The temperature is obtained from the PL SYSMONE4 primitive and consists of a 16 bit raw value. This value can also be accessed by the software using the TEMPERATURE register however the reading is done periodically and overwrites the register so only the most value will be available. In order to keep the IP as light as possible, the value obtained from the SYSMONE4 primitive is used as raw, it is not converted to Celsius. In order to convert to Celsius the following formula needs to be used:

Temperature [C] = (ADC × 501.3743 / 2^bits) – 273.6777 ug580

There are five configurations described in the hardware, each with a corresponding tacho period +/- 25% tolerance.

*The tacho parameters are for a SUNON PF92251B1-000U-S99 fan

PWM duty-cycle	Nominal tacho period	Tacho tolerance 25%
0%	N/A	N/A
25%	32 ms	8ms
50%	12.8 ms	3.2 ms
75%	7.2 ms	1.8 ms
100%	6.4 ms	1.6 ms

The hardware will evaluate the tacho signal based on the current PWM duty-cycle by comparing the measured value with the interval's thresholds. i.e. at 50% duty-cycle the tacho period must stay within 9.6 ms and 16 ms.

A time-out is also used to check if there is any tacho signal at all.

Software control and customization

The software can request a different PWM duty-cycle by using the provided registers. All of the values inside the PWM/TACHO registers are in clock-cycle periods. It can also provide different tacho parameters if it wants to continue to evaluate the tacho signal. The PWM period can be read from the PWM_PERIOD register and is by default 20000.

i.e. 5KHz → 20000 * 10 ns = 200 us

The software may request a different PWM duty-cycle if needed by writing to the PWM_WIDTH register. The new value must be greater or equal to the value selected by the hardware and less or equal to the PWM period. The software can use the PWM_WIDTH and PWM_PERIOD registers in order to make sure the new value is valid.

After requesting a new duty-cycle there is a 5 second delay during which the hardware waits for the fan rotaion speed to stabilize. The software will then have to provide parameters for the tacho signal in order for the hardware to be able to evaluate it. To do this the software will have to write the TACHO_PERIOD and TACHO_TOLERANCE registers in that order. The software can read the TACHO_MEASUREMENT register to obtain the new tacho period and derive the tolerance value from it.

A mearsurement is performed by averaging 128 consecutive tacho perdiod measurements. The time needed to finish a measurement depends on the frequency of the signal.

The software can now use this register to read the new tacho pediod and then write it to the TACHO_PERIOD register. Then it can write a tolerance value to the TACHO_TOLERANCE register. The hardware will only start to monitor the tacho signal when the tolerance is provided.

Interrupts

The fan controller supports interrupts to both inform the software of any possible errors and also to facilitate the control of the core. There are four interrupt sources:

The PWM_CHANGED interrupt is generated at the end of the 5 second delay after a PWM duty-cycle change request. The request can come either from the software or from the hardware
The TEMP_INCREASE occurs when the hardware requests a higher PWM width than the curret one, indicating a rise in temperature.
NEW_TACHO_MEASUREMENT is asserted when a tacho measurement cycle is completed and the value is written to the TACHO_MEASUREMENT register. The software can use this interrupt in the process where it requests a new PWM width in order to obtain tacho information.
The TACHO_ERR interrupt is generated when the tacho signal either fails to stay within its designated frequency interval or does not toggle at all for 5 seconds.

Wiki

Analog Devices Wiki

Table of Contents

Fan Control IP Core

Block Diagram

Introduction

Configuration Parameter

Signal and Interface Pins

Register Map

Fan Controller (axi_fan_control)

Clocking

Theory of Operation

Running independently

Software control and customization

Interrupts

Analog Devices Wiki

Table of Contents

Fan Control IP Core

Block Diagram

Introduction

Configuration Parameter

Signal and Interface Pins

Register Map

Fan Controller (axi_fan_control)

Clocking

Theory of Operation

Running independently

Software control and customization

Interrupts

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