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resources:fpga:docs:axi_adxcvr [12 Feb 2019 10:07] – Improved SYSCLK_SEL description Adrian Costinaresources:fpga:docs:axi_adxcvr [01 Oct 2019 16:45] – Add device spec registers Andrei Grozav
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 ^0x0005 ^0x0014 ^REG_STATUS ^^^Status Reporting Register ^ ^0x0005 ^0x0014 ^REG_STATUS ^^^Status Reporting Register ^
 | | |[0] |STATUS |RO | After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation. | | | |[0] |STATUS |RO | After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation. |
 +^0x0007 ^0x001c ^REG_FPGA_INFO ^^^FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl |Intel encoded values]] [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]] ^
 +| | |[31:24] |FPGA_TECHNOLOGY |RO |Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
 +| | |[23:16] |FPGA_FAMILY |RO |Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
 +| | |[15:8] |SPEED_GRADE |RO |Encoded value describing the FPGA's speed-grade |
 +| | |[7:0] |DEV_PACKAGE |RO |Encoded value describing the device package. The package might affect high-speed interfaces |
 ^0x0008 ^0x0020 ^REG_CONTROL ^^^Transceiver Control Register ^ ^0x0008 ^0x0020 ^REG_CONTROL ^^^Transceiver Control Register ^
 | | |[12] |LPM_DFE_N |RW | Transceiver primitive control, refer Xilinx documentation. | | | |[12] |LPM_DFE_N |RW | Transceiver primitive control, refer Xilinx documentation. |
 | | |[10:8] |RATE[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. | | | |[10:8] |RATE[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. |
-| | |[5:4] |SYSCLK_SEL[1:0] |RW | Transceiver primitive control, refer Xilinx documentation. It controls the [RX/TX]SYSCLKSEL for 7 Series devices and [RX/TX]PLLCLKSEL and also[RX/TX]SYSCLKSEL for Ultrascale(+) devices. |+| | |[5:4] |SYSCLK_SEL[1:0] |RW | Transceiver primitive control, refer Xilinx documentation. |
 | | |[2:0] |OUTCLK_SEL[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. | | | |[2:0] |OUTCLK_SEL[2:0] |RW | Transceiver primitive control, refer Xilinx documentation. |
 ^0x0010 ^0x0040 ^REG_CM_SEL ^^^Transceiver Access Register ^ ^0x0010 ^0x0040 ^REG_CM_SEL ^^^Transceiver Access Register ^
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 ^0x0032 ^0x00c8 ^REG_TX_PRECURSOR ^^^Transceiver primitive control, refer Xilinx documentation. ^ ^0x0032 ^0x00c8 ^REG_TX_PRECURSOR ^^^Transceiver primitive control, refer Xilinx documentation. ^
 | | |[31:0] |REG_TX_PRECURSOR[31:0] |RW | Transmiter pre-cursor TX pre-emphasis control. | | | |[31:0] |REG_TX_PRECURSOR[31:0] |RW | Transmiter pre-cursor TX pre-emphasis control. |
 +^0x0050 ^0x0140 ^REG_FPGA_VOLTAGE ^^^FPGA device voltage information ^
 +| | |[15:0] |FPGA_VOLTAGE |RO |The voltage of the FPGA device in mv |
 ===== Software Guidelines ===== ===== Software Guidelines =====
  
resources/fpga/docs/axi_adxcvr.txt · Last modified: 04 Feb 2022 09:11 by Michael Hennerich

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