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resources:fpga:docs:axi_adc_trigger [26 Mar 2019 13:39] – Update [Register Map] Andrei Grozavresources:fpga:docs:axi_adc_trigger [13 Oct 2021 09:56] (current) – Edit footer & add reference to generic ADC Iulia Moldovan
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-===== AXI_ADC_TRIGGER =====+====== AXI_ADC_TRIGGER ======
  
-The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.+The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]].
  
-==== Features ====+ 
 +===== Features =====
  
   * AXI Lite control/status interface   * AXI Lite control/status interface
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     * Falling edge     * Falling edge
   * Mixing analog and digital triggers   * Mixing analog and digital triggers
 +  * Instrument trigger (from Logic Analyzer)
   * Controls two IO trigger pins   * Controls two IO trigger pins
  
-==== Block Diagram ====+ 
 +===== Block Diagram =====
  
 {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}} {{:resources:fpga:docs:axi_adc_trigger_diagram.png?600|}}
-==== Interface ====+ 
 +==== AXI ADC Tigger submodules ==== 
 + 
 +  * [[:resources:fpga:docs:axi_adc_trigger#register_map | Register-map ]] 
 +  * **Channel trigger** 
 +    * Channel A 
 +      * Amplitude limit - REG_LIMIT_A(0x0014) - Defines the treashold level for the ADC trigger 
 +      * Function - TRIGGER_FUNCTION_A(0x0018) - Lower, higher than limit; pass through limit 
 +      * Hysteresis - TRIGGER_FUNCTION_A (0x001c) - "+-" value. Used for the passthrough functions 
 +    * Channel B 
 +      * Amplitude limit - REG_LIMIT_A(0x0024) - Defines the treashold level for the ADC trigger 
 +      * Function - TRIGGER_FUNCTION_A(0x0028) - Lower, higher than limit; pass through limit 
 +      * Hysteresis - TRIGGER_FUNCTION_A (0x002c) - "+-" value. Used for the passthrough functions 
 + 
 +  * **External trigger** 
 +    * Pin 0 (Ti) \\ Configurations - REG_CONFIG_TRIGGER_I(0x004) allows for: 
 +      * falling edge (bit 8) 
 +      * rising edge  (bit 6) 
 +      * any edge     (bit 4) 
 +      * high level   (bit 2) 
 +      * low level    (bit 0) 
 +    * Pin 1 (To) \\ Configurations - REG_CONFIG_TRIGGER_I(0x004) allows for: 
 +      * falling edge (bit 9) 
 +      * rising edge  (bit 7) 
 +      * any edge     (bit 5) 
 +      * high level   (bit 3) 
 +      * low level    (bit 1) 
 + 
 +<note important>In the case of M2k, the trigger pins(Ti and To) are chosen one for input and one for output. This is for the ease of configuring a daisy-chain of M2k's. The hardware and software support both pins to be configured as input or output in REG_IO_SELECTION(0x000c)</note> 
 +  
 +  * **Channel A MUX** - REG_TRIGGER_MUX_A(0x0020) - Selects between a combination of ADC trigger and the external trigger 
 +  * **Channel B MUX** - REG_TRIGGER_MUX_B(0x0030) - Selects between a combination of ADC trigger and the external trigger 
 + 
 +  * **Output MUX** - REG_TRIGGER_OUT_CONTROL(0x0034) - Selects a combination between the channel A and/or B MUX's and the input of the instrument trigger 
 +  * **Holdoff counter** (32 bit) - REG_TRIGGER_HOLDOFF(0x0048) - Controls the trigger out silent period after an event.  
 +  * **Delay counter** (32 bit) - REG_TRIGGER_DELAY(0x0040) - Controls the trigger delay  
 + 
 +  * **External trigger control** 
 +      * REG_IO_SELECTION(0x000c) - Controls the direction of the external trigger pins, and the source(for each pin configured as output) 
 +      * REG_TRIGGER_OUT_HOLD_PINS(0x004c) - Controls the hold period after a transition to a new logic level. 
 + 
 + 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 |              | ''data_valid_a_trig'' | ''output'' | Data valid for channel A | |              | ''data_valid_a_trig'' | ''output'' | Data valid for channel A |
 |              | ''data_valid_b_trig'' | ''output'' | Data valid for channel B | |              | ''data_valid_b_trig'' | ''output'' | Data valid for channel B |
 +|              | ''trigger_out'' | ''output'' | trigger out of the adc_trigger delayed by 4 clock cycles plus the trigger delay mechanism used with the variable fifo for history(data before trigger) |
 +|              | ''trigger_out_la'' | ''output'' | trigger out of the adc_trigger delayed by 2 clock cycles minimum possible delay for instrument trigger |
 | **Fifo Depth** |||| | **Fifo Depth** ||||
 |              |''fifo_depth'' | ''output[31:0]'' | Controls the dynamic depth of the history FIFO | |              |''fifo_depth'' | ''output[31:0]'' | Controls the dynamic depth of the history FIFO |
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 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
  
-==== Detailed Description ==== 
  
-The AXI_ADC_TRIGGER IP implements triggering for the ADC path based on two trigger pins or based on the analog channel.+===== Detailed Description =====
  
-The trigger pins are controlled by the core and can be both input or output. For external triggering, they must be set to inputs.+The AXI_ADC_TRIGGER IP implements triggering for the ADC path. The trigger is generated based on two external trigger pins, a triggering signal from the logic analyzer and the ADC channels.
  
-The analog triggering is based on comparison with a limit. The data format must be 2's complement and maximum number of bits of the analog channel is 15. +The external trigger pins are controlled by the core and can be both input or output. For external triggering, they must be set to inputs(independently).
-The trigger is embedded in the output word, at bit 15. Before forwarding the data to the DMA, the triggers must be extracted and data must be reconstructed. The UTIL_EXTRACT IP can be used for this purpose. +
-Embedding the trigger with the data allows for additional IPs with unknown pipeline length to be introduced in the path.+
  
-If a history for data before the trigger is needed to be transfered, a variable FIFO IP should be used. The FIFO depth is controlled using the trigger_offset bus of this IP.+The analog triggering is based on comparison with a limit. The data format must be 2's complement and the maximum number of bits of the analog channel is 15. 
 +The trigger can be transmitted independent or embedded in the output word, at bit 15. When embedded, the triggers must be extracted and data must be reconstructed, before forwarding the data to the DMA. The UTIL_EXTRACT IP can be used for this purpose. 
 +Embedding the trigger in the data allows for additional IPs with unknown pipeline length to be introduced in the path.
  
-==== Register Map ====+If a history for data before the trigger is needed, a [[:resources:fpga:docs:util_var_fifo | variable FIFO IP ]] should be used. The FIFO depth is controlled using the trigger_offset bus of this IP. 
 + 
 + 
 +===== Register Map =====
  
 |< 100% 5% 5% 5% 25% 5% 5% 50% >| |< 100% 5% 5% 5% 25% 5% 5% 50% >|
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 |::: |::: |[0] |TRIGGER_O[0] |RW |0x00 |Set TRIGGER_O[0] value | |::: |::: |[0] |TRIGGER_O[0] |RW |0x00 |Set TRIGGER_O[0] value |
 ^0x0003 ^0x000c ^REG_IO_SELECTION ^^^^Control Trigger Pins Direction ^ ^0x0003 ^0x000c ^REG_IO_SELECTION ^^^^Control Trigger Pins Direction ^
-| | |[7:5] |TRIGGER_O[1] (PIN) |RW |0x00 |Select output trigger pin 1 \\   0: SOFTWARE TRIGGER - TRRIGER_O[1](0x0004) \\   1: TRIGGER_I[1] (PIN) \\   2: TRIGGER_I[0] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | +| | |[7:5] |TRIGGER_O[1] (To PIN) |RW |0x00 |Select output trigger pin 1 \\   0: SOFTWARE TRIGGER - TRRIGER_O[1](0x0004) \\   1: TRIGGER_I[1] (PIN) \\   2: TRIGGER_I[0] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | 
-|::: |::: |[4:2] |TRIGGER_O[0] (PIN) |RW |0x00 |Select output trigger pin 0 \\   0: SOFTWARE TRIGGER - TRRIGER_O[0](0x0004) \\   1: TRIGGER_I[0] (PIN) \\   2: TRIGGER_I[1] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | +|::: |::: |[4:2] |TRIGGER_O[0] (Ti PIN) |RW |0x00 |Select output trigger pin 0 \\   0: SOFTWARE TRIGGER - TRRIGER_O[0](0x0004) \\   1: TRIGGER_I[0] (PIN) \\   2: TRIGGER_I[1] (PIN) \\   3: TRIGGER_OUT (axi_adc_trigger)   4: TRIGGER_IN (Logic analyzer) \\ | 
-|::: |::: |[1] |IO_SELECTION[1] |RW |0x00 |Drives the TRIGGER_T[1] pin | +|::: |::: |[1] |IO_SELECTION[1] |RW |0x00 |Drives the TRIGGER_T[1](To) pin | 
-|::: |::: |[0] |IO_SELECTION[0] |RW |0x00 |Drives the TRIGGER_T[0] pin |+|::: |::: |[0] |IO_SELECTION[0] |RW |0x00 |Drives the TRIGGER_T[0](Ti) pin |
 ^0x0004 ^0x0010 ^REG_CONFIG_TRIGGER_I ^^^^Configure Digital Triggering ^ ^0x0004 ^0x0010 ^REG_CONFIG_TRIGGER_I ^^^^Configure Digital Triggering ^
 | | |[9:8] |FALL_EDGE |RW |0x00 |Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin | | | |[9:8] |FALL_EDGE |RW |0x00 |Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin |
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 ^0x0006 ^0x0018 ^REG_FUNCTION_A ^^^^Analog Triggering Function ^ ^0x0006 ^0x0018 ^REG_FUNCTION_A ^^^^Analog Triggering Function ^
 | | |[1:0] |TRIGGER_FUNCTION_A |RW |0x00 |Analog triggering function for channel A: \\   0: Lower than limit \\   1: higher than limit \\   2: pass through high limit \\   3: passthrough low limit | | | |[1:0] |TRIGGER_FUNCTION_A |RW |0x00 |Analog triggering function for channel A: \\   0: Lower than limit \\   1: higher than limit \\   2: pass through high limit \\   3: passthrough low limit |
-^0x0007 ^0x001c ^REG_HYSTERESIS_A ^^^^Analog Trigger Histeresys for Channel ^ +^0x0007 ^0x001c ^REG_HYSTERESIS_A ^^^^Analog Trigger Hysteresis for Channel ^ 
-| | |[31:0] |HISTERESYS_A |RW |0x00 |Used for the passthrough functions |+| | |[31:0] |HYSTERESIS_A |RW |0x00 |Used for the passthrough functions |
 ^0x0008 ^0x0020 ^REG_TRIGGER_MUX_A ^^^^Trigger Selection for Path ^ ^0x0008 ^0x0020 ^REG_TRIGGER_MUX_A ^^^^Trigger Selection for Path ^
 | | |[3:0] |TRIGGER_MUX_A |RW |0x00 |Selects trigger a mode: \\   0: Always on \\   1: Digital triggering, based on trigger[0] \\   2: ADC triggering, based on channel A \\   3: Reserved \\   4: Digital triggering OR ADC triggering \\   5: Digital triggering AND ADC triggering \\   6: Digital triggering XOR ADC triggering \\   7: Option 4 negated \\   8: Option 5 negated \\   9: Option 6 negated | | | |[3:0] |TRIGGER_MUX_A |RW |0x00 |Selects trigger a mode: \\   0: Always on \\   1: Digital triggering, based on trigger[0] \\   2: ADC triggering, based on channel A \\   3: Reserved \\   4: Digital triggering OR ADC triggering \\   5: Digital triggering AND ADC triggering \\   6: Digital triggering XOR ADC triggering \\   7: Option 4 negated \\   8: Option 5 negated \\   9: Option 6 negated |
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 ^0x000A ^0x0028 ^REG_FUNCTION_B ^^^^Analog Triggering Function ^ ^0x000A ^0x0028 ^REG_FUNCTION_B ^^^^Analog Triggering Function ^
 | | |[1:0] |TRIGGER_FUNCTION_B |RW |0x00 |Analog triggering function for channel B: \\   0: Lower than limit \\   1: higher than limit \\   2: pass through high limit \\   3: passthrough low limit | | | |[1:0] |TRIGGER_FUNCTION_B |RW |0x00 |Analog triggering function for channel B: \\   0: Lower than limit \\   1: higher than limit \\   2: pass through high limit \\   3: passthrough low limit |
-^0x000B ^0x002c ^REG_HYSTERESIS_B ^^^^Analog Trigger Histeresys for Channel ^ +^0x000B ^0x002c ^REG_HYSTERESIS_B ^^^^Analog Trigger Hysteresis for Channel ^ 
-| | |[31:0] |HISTERESYS_B |RW |0x00 |Used for the passthrough functions |+| | |[31:0] |HYSTERESIS_B |RW |0x00 |Used for the passthrough functions |
 ^0x000C ^0x0030 ^REG_TRIGGER_MUX_B ^^^^Trigger Selection for Path ^ ^0x000C ^0x0030 ^REG_TRIGGER_MUX_B ^^^^Trigger Selection for Path ^
 | | |[3:0] |TRIGGER_MUX_B |RW |0x00 |Selects trigger B mode: \\   0: Always on \\   1: Digital triggering, based on trigger[1] \\   2: ADC triggering, based on channel B \\   3: Reserved \\   4: Digital triggering OR ADC triggering \\   5: Digital triggering AND ADC triggering \\   6: Digital triggering XOR ADC triggering \\   7: Option 4 negated \\   8: Option 5 negated \\   9: Option 6 negated | | | |[3:0] |TRIGGER_MUX_B |RW |0x00 |Selects trigger B mode: \\   0: Always on \\   1: Digital triggering, based on trigger[1] \\   2: ADC triggering, based on channel B \\   3: Reserved \\   4: Digital triggering OR ADC triggering \\   5: Digital triggering AND ADC triggering \\   6: Digital triggering XOR ADC triggering \\   7: Option 4 negated \\   8: Option 5 negated \\   9: Option 6 negated |
 ^0x000D ^0x0034 ^REG_TRIGGER_OUT_CONTROL ^^^^Selection Multiplexer and embedded trigger selection ^ ^0x000D ^0x0034 ^REG_TRIGGER_OUT_CONTROL ^^^^Selection Multiplexer and embedded trigger selection ^
 | | |[16] |EMBEDDE_TRIGGER |RW |0x00 |When set the bit 15 of the out channel data will be the trigger. This alows to keep the data in sync with the trigger in future data processing, before feeding the data to the DMA.\\ When set a util_extract module is required in the system. | | | |[16] |EMBEDDE_TRIGGER |RW |0x00 |When set the bit 15 of the out channel data will be the trigger. This alows to keep the data in sync with the trigger in future data processing, before feeding the data to the DMA.\\ When set a util_extract module is required in the system. |
-|::: |::: |[3:0] |TRIGGER_MUX_OUT |RW |0x00 |Final Trigger Selection Multiplexer \\ Selects trigger a mode: \\   0: Trigger A \\   1: Trigger B \\   2: Trigger A OR Trigger B \\   3: Trigger A AND Trigger B \\   4: Trigger A XOR Trigger B \\   1: Trigger CASCADED \\   4: Trigger A OR Trigger CASCADED \\   4: Trigger B OR Trigger CASCADED \\   4: Trigger A OR Trigger B OR Trigger CASCADED |+|::: |::: |[3:0] |TRIGGER_MUX_OUT |RW |0x00 |Final Trigger Selection Multiplexer \\ Selects trigger a mode: \\   0: Trigger A \\   1: Trigger B \\   2: Trigger A OR Trigger B \\   3: Trigger A AND Trigger B \\   4: Trigger A XOR Trigger B \\   5: Trigger LA \\   6: Trigger A OR Trigger LA \\   7: Trigger B OR Trigger LA \\   8: Trigger A OR Trigger B OR Trigger LA |
 ^0x000E ^0x0038 ^REG_FIFO_DEPTH ^^^^Controls the Dynamic Depth of the History FIFO ^ ^0x000E ^0x0038 ^REG_FIFO_DEPTH ^^^^Controls the Dynamic Depth of the History FIFO ^
 | | |[31:0] |FIFO_DEPTH |RW |0x00 |Controls the depth of the history FIFO. Should be less than the maximum FIFO depth. If set to 0, the FIFO is bypassed. | | | |[31:0] |FIFO_DEPTH |RW |0x00 |Controls the depth of the history FIFO. Should be less than the maximum FIFO depth. If set to 0, the FIFO is bypassed. |
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 | | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. | | | |[31:0] |TRIGGER_DELAY |RW |0x00 |Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. |
 ^0x0011 ^0x0044 ^REG_STREAMING ^^^^Controls Streaming Mode ^ ^0x0011 ^0x0044 ^REG_STREAMING ^^^^Controls Streaming Mode ^
-| | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuosly  captured by the DMA. The streaming bit must be set to 0 to reset triggering.  | +| | |[0] |STREAMING |RW |0x00 |If the streaming bit is set, after the trigger condition is met data will be continuously captured by the DMA. The streaming bit must be set to 0 to reset triggering.  | 
-^Tue Mar 26 12:35:27 2019 ^^^^^^+^0x0012 ^0x0048 ^REG_TRIGGER_HOLDOFF ^^^^Controls hold off time ^ 
 +| | |[31:0] |TRIGGER_HOLDOFF |RW |0x00 |Defines the time interval, after a trigger event, where the next trigger events will be ignored, until the end of the interval. The time interval is set by counter. Down-counting on the ADC clock(100MHz). The value written in the register is loaded in the counter at a trigger event. | 
 +^0x0013 ^0x004c ^REG_TRIGGER_OUT_HOLD_PINS ^^^^Controls external trigger hold time ^ 
 +| | |[19:0] |TRIGGER_OUT_HOLD_PINS |RW |0x00 |Defines a time period, in which the external trigger pins, configured as outputs, will hold the new logic level after a transition. The down-counter, counting on ADC clock, is loaded with the value written in the register after a new transition of the source trigger signal, if the counter is inactive. | 
 +^Tue Sep  1 09:58:53 2020 ^^^^^^ 
 + 
 + 
 +===== Aditional notes ===== 
 + 
 +<note important>Instrument triggering in only available from major version 3.</note> 
 + 
 + 
 +===== References =====
  
-==== References ==== +  * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\ 
-  * [[https://github.com/analogdevicesinc/hdl/tree/dev/library/axi_adc_trigger | AXI_ADC_TRIGGER source code]] \\ +  * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
-  * [[https://wiki.analog.com/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\+
   * [[https://github.com/analogdevicesinc/linux/tree/m2k | ADI Linux repository ]]   * [[https://github.com/analogdevicesinc/linux/tree/m2k | ADI Linux repository ]]
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Tips}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_adc_trigger.1553603954.txt.gz · Last modified: 26 Mar 2019 13:39 by Andrei Grozav

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