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resources:fpga:docs:axi_adc_decimate [04 Aug 2017 13:35] – Added scale correction related registers Adrian Costina | resources:fpga:docs:axi_adc_decimate [14 Dec 2023 17:02] (current) – Update max real bits to 12. Andrei Grozav | ||
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- | ===== AXI_ADC_DECIMATE ===== | + | ====== AXI_ADC_DECIMATE |
- | The AXI_ADC_DECIMATE IP allows decimating of the input data by 10/ | + | The AXI_ADC_DECIMATE IP allows decimating of the input data by 10/ |
+ | \\ | ||
+ | More about the generic framework interfacing ADCs can be read here: [[: | ||
- | ==== Features ==== | + | <note important> |
+ | |||
+ | ===== Features | ||
* AXI Lite control/ | * AXI Lite control/ | ||
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* Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter. | * Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter. | ||
- | ==== Block Diagram ==== | + | |
+ | ===== Block Diagram | ||
{{ : | {{ : | ||
- | ==== Interface ==== | + | |
+ | ==== Configuration Parameters ===== | ||
+ | |||
+ | ^ Name ^ Description ^ Default Value^ | ||
+ | | '' | ||
+ | |||
+ | |||
+ | ===== Interface | ||
^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
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| | '' | | | '' | ||
| | '' | | | '' | ||
+ | | | '' | ||
+ | | | '' | ||
| **AXI_S_MM interface** |||| | | **AXI_S_MM interface** |||| | ||
| | '' | | | '' | ||
- | ==== Detailed Description ==== | ||
- | For some applications, | + | ===== Detailed Description ===== |
+ | |||
+ | For some applications, | ||
The decimation block allows decimating the input data so that the sampling frequency to be reduced by 10, 100, 1000, 10000, 100000, with filtering. | The decimation block allows decimating the input data so that the sampling frequency to be reduced by 10, 100, 1000, 10000, 100000, with filtering. | ||
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At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering. | At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering. | ||
- | ==== Register Map ==== | + | |
+ | ===== Register Map ===== | ||
|< 100% 5% 5% 5% 25% 5% 55% >| | |< 100% 5% 5% 5% 25% 5% 55% >| | ||
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| | |[15:0] |CORRECTION_COEFFICIENT |RW |Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification. | | | | |[15:0] |CORRECTION_COEFFICIENT |RW |Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification. | | ||
- | ==== References ==== | ||
- | * [[https:// | ||
- | * [[https:// | ||
- | * [[https:// | ||
- | * [[http:// | ||
- | {{navigation #axi_ip|AXI IP#hdl|Main page#tips|Tips}} | + | ===== References ===== |
+ | * [[https:// | ||
+ | * [[/ | ||
+ | * [[https:// | ||
+ | * [[xilinx> | ||
+ | |||
+ | {{navigation |