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resources:fpga:docs:axi_adc_decimate [11 Oct 2021 15:10] – Edit footer Iulia Moldovanresources:fpga:docs:axi_adc_decimate [13 Oct 2021 09:51] – Edit footer & add reference to generic ADC Iulia Moldovan
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-===== AXI_ADC_DECIMATE =====+====== AXI_ADC_DECIMATE ======
  
-The AXI_ADC_DECIMATE IP allows decimating of the input data by 10/100/1000/10000/100000, with filtering and arbitrary decimation by dropping samples.+The AXI_ADC_DECIMATE IP allows decimating of the input data by 10/100/1000/10000/100000, with filtering and arbitrary decimation by dropping samples.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]].
  
-==== Features ====+ 
 +===== Features =====
  
   * AXI Lite control/status interface   * AXI Lite control/status interface
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   * Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter.   * Filtering is implemented by a 6 sections CIC programmable rate filter and a compensation FIR filter.
  
-==== Block Diagram ====+ 
 +===== Block Diagram =====
  
 {{ :resources:fpga:docs:axi_adc_decimate.svg | AXI_ADC_DECIMATE Block diagram }} {{ :resources:fpga:docs:axi_adc_decimate.svg | AXI_ADC_DECIMATE Block diagram }}
  
-=== Configuration Parameters ====+ 
 +==== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
 | ''CORRECTION_DISABLE'' | Disable scale correction of the CIC output | 1 | | ''CORRECTION_DISABLE'' | Disable scale correction of the CIC output | 1 |
  
-==== Interface ====+ 
 +===== Interface =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
  
-==== Detailed Description ====+ 
 +===== Detailed Description =====
  
 For some applications, the maximum sampling rate is not required and leads to lots of samples transferred to memory. In order to avoid that, the decimation IP is used. For some applications, the maximum sampling rate is not required and leads to lots of samples transferred to memory. In order to avoid that, the decimation IP is used.
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 At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering. At the end of the filter chain, there is an arbitrary decimation block. The arbitrary decimation can be activated independently and it does not implement any type of filtering.
  
-==== Register Map ====+ 
 +===== Register Map =====
  
 |< 100% 5% 5% 5% 25% 5% 55% >| |< 100% 5% 5% 5% 25% 5% 55% >|
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 | | |[15:0] |CORRECTION_COEFFICIENT |RW |Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification. | | | |[15:0] |CORRECTION_COEFFICIENT |RW |Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, integer and fractional bits). Allows for correction of the CIC filter amplification. |
  
-==== References ====+ 
 +===== References =====
   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_decimate| AXI_ADC_DECIMATE IP source code]] \\   * [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_adc_decimate| AXI_ADC_DECIMATE IP source code]] \\
   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\   * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\
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   * [[xilinx>support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] \\   * [[xilinx>support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf | 7 Series libraries]] \\
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_adc_decimate.txt · Last modified: 14 Dec 2023 17:02 by Andrei Grozav

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