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resources:fpga:docs:axi_ad9671 [11 Oct 2021 14:41] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:axi_ad9671 [13 Oct 2021 09:48] – Edit footer & add reference to generic ADC Iulia Moldovan
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 The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9671|axi_ad9671]] IP core can be used to interface the [[adi>AD9671]] Octal Ultrasound AFE with digital demodulator. The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9671|axi_ad9671]] IP core can be used to interface the [[adi>AD9671]] Octal Ultrasound AFE with digital demodulator.
-An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP.+An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP.\\ 
 +\\ 
 +More about the generic framework interfacing ADCs can be read here: [[:resources:fpga:docs:axi_adc_ip]]. 
  
 ===== Features ===== ===== Features =====
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   * Altera Quartus compatible \\   * Altera Quartus compatible \\
   * Xilinx Vivado compatible \\   * Xilinx Vivado compatible \\
 +
  
 ===== Block Diagram ===== ===== Block Diagram =====
  
 {{  :resources:fpga:docs:adc_jesd.svg | AXI_AD9671 Block diagram }} {{  :resources:fpga:docs:adc_jesd.svg | AXI_AD9671 Block diagram }}
 +
  
 ===== Configuration Parameter ===== ===== Configuration Parameter =====
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 | ''DEVICE_TYPE'' | Selection between Xilinx(0) and Altera(1) devices| 0 | | ''DEVICE_TYPE'' | Selection between Xilinx(0) and Altera(1) devices| 0 |
 | ''QUAD_OR_DUAL_N'' | Selects if 4 lanes (1) or 2 lanes (0) are connected | 1 | | ''QUAD_OR_DUAL_N'' | Selects if 4 lanes (1) or 2 lanes (0) are connected | 1 |
 +
  
 ===== Interface ===== ===== Interface =====
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 |              | ''adc_raddr_in'' | ''input[3:0]'' | Read address. All IPs are sending data from the same memory location. Comes from the master IP| |              | ''adc_raddr_in'' | ''input[3:0]'' | Read address. All IPs are sending data from the same memory location. Comes from the master IP|
 |              | ''adc_raddr_out'' | ''output[3:0]'' | Read address. All IPs are sending data from the same memory location. Sent to the slave IPs | |              | ''adc_raddr_out'' | ''output[3:0]'' | Read address. All IPs are sending data from the same memory location. Sent to the slave IPs |
 +
  
 ===== Detailed Architecture ===== ===== Detailed Architecture =====
  
 {{  :resources:fpga:docs:ad9671.svg | AXI_AD9671 IP architecture?800x600}} {{  :resources:fpga:docs:ad9671.svg | AXI_AD9671 IP architecture?800x600}}
- 
 \\ \\
 +
 ===== Detailed Description ===== ===== Detailed Description =====
  
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   * the ADC CHANNEL register map \\   * the ADC CHANNEL register map \\
  
-===== Register Map ===== 
  
 +===== Register Map =====
  
 {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
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 {{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}}
 +
  
 ===== Design Guidelines ===== ===== Design Guidelines =====
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 If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level). If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).
 +
  
 ===== References ===== ===== References =====
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   * [[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf | 7 Series transceivers]] \\   * [[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf | 7 Series transceivers]] \\
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}} +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
- +
resources/fpga/docs/axi_ad9671.txt · Last modified: 25 Apr 2023 09:42 by Iulia Moldovan

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