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resources:fpga:docs:axi_ad9671 [14 Jan 2021 05:24] – use / xilinx> interwiki links Robin Getz | resources:fpga:docs:axi_ad9671 [13 Oct 2021 09:48] – Edit footer & add reference to generic ADC Iulia Moldovan | ||
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The [[https:// | The [[https:// | ||
- | An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP. | + | An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP.\\ |
+ | \\ | ||
+ | More about the generic framework interfacing ADCs can be read here: [[: | ||
===== Features ===== | ===== Features ===== | ||
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* Altera Quartus compatible \\ | * Altera Quartus compatible \\ | ||
* Xilinx Vivado compatible \\ | * Xilinx Vivado compatible \\ | ||
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===== Block Diagram ===== | ===== Block Diagram ===== | ||
{{ : | {{ : | ||
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===== Configuration Parameter ===== | ===== Configuration Parameter ===== | ||
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| '' | | '' | ||
| '' | | '' | ||
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===== Interface ===== | ===== Interface ===== | ||
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| | '' | | | '' | ||
| | '' | | | '' | ||
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===== Detailed Architecture ===== | ===== Detailed Architecture ===== | ||
{{ : | {{ : | ||
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\\ | \\ | ||
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===== Detailed Description ===== | ===== Detailed Description ===== | ||
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* the ADC CHANNEL register map \\ | * the ADC CHANNEL register map \\ | ||
- | ===== Register Map ===== | ||
+ | ===== Register Map ===== | ||
{{page>: | {{page>: | ||
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{{page>: | {{page>: | ||
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===== Design Guidelines ===== | ===== Design Guidelines ===== | ||
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If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level). | If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level). | ||
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===== References ===== | ===== References ===== | ||
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* [[xilinx> | * [[xilinx> | ||
- | {{navigation #axi_ip|AXI IP#hdl|Main page#util_ip|UTIL IP Cores}} | + | {{navigation |
- | + |