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| resources:fpga:docs:axi_ad9361 [10 Feb 2020 14:50] – [References] Fix AD9361 IP link Stanca-Florina Pop | resources:fpga:docs:axi_ad9361 [04 Mar 2020 14:58] – Fix broken links Stanca-Florina Pop |
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| The axi_ad9361 cores architecture contains: \\ | The axi_ad9361 cores architecture contains: \\ |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361.v#L302|Interface]] module in either CMOS or LVDS mode for [[https://github.com/analogdevicesinc/hdl/tree/dev/library/axi_ad9361/altera|Altera]] or [[https://github.com/analogdevicesinc/hdl/tree/dev/library/axi_ad9361/xilinx|Xilinx]] devices. \\ | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361.v#L302|Interface]] module in either CMOS or LVDS mode for [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/altera|Altera]] or [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9361/xilinx|Xilinx]] devices. \\ |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_rx.v|Receive]] module, which contains: | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx.v|Receive]] module, which contains: |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_rx_channel.v|ADC channel processing]] modules, one for each channel \\ | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx_channel.v|ADC channel processing]] modules, one for each channel \\ |
| * data processing modules ([[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/ad_dcfilter.v|DC filter]], [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/ad_iqcor.v|IQ Correction]] and [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/ad_datafmt.v|Data format control]]) | * data processing modules ([[https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dcfilter.v|DC filter]], [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_iqcor.v|IQ Correction]] and [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_datafmt.v|Data format control]]) |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_rx_pnmon.v|ADC PN Monitor]] for interface validation \\ | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_rx_pnmon.v|ADC PN Monitor]] for interface validation \\ |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_adc_channel.v|ADC Channel register map]] | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_adc_channel.v|ADC Channel register map]] |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_delay_cntrl.v|Delay Control]] and [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_adc_common.v|ADC Common register map]] | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_delay_cntrl.v|Delay Control]] and [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_adc_common.v|ADC Common register map]] |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_tx.v|Transmit]] module, which contains: | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_tx.v|Transmit]] module, which contains: |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_tx_channel.v|DAC channel processing]] modules, one for each channel \\ | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_tx_channel.v|DAC channel processing]] modules, one for each channel \\ |
| * Different data generators ([[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/ad_dds.v|DDS]], pattern, PRBS) | * Different data generators ([[https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_dds.v|DDS]], pattern, PRBS) |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/ad_iqcor.v|IQ Correction]] | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/ad_iqcor.v|IQ Correction]] |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_dac_channel.v|DAC Channel register map]] | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_dac_channel.v|DAC Channel register map]] |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_delay_cntrl.v|Delay Control]] and [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_dac_common.v|DAC Common register map]] | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_delay_cntrl.v|Delay Control]] and [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_dac_common.v|DAC Common register map]] |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9361/axi_ad9361_tdd.v|TDD control module]] for TDD mode, see more information on the [[https://wiki.analog.com/resources/eval/user-guides/ad-pzsdr2400tdd-eb/reference_hdl|HDL support for AD9361 TDD mode]] wiki page. | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/axi_ad9361/axi_ad9361_tdd.v|TDD control module]] for TDD mode, see more information on the [[https://wiki.analog.com/resources/eval/user-guides/ad-pzsdr2400tdd-eb/reference_hdl|HDL support for AD9361 TDD mode]] wiki page. |
| * [[https://github.com/analogdevicesinc/hdl/blob/dev/library/common/up_axi.v|AXI control and status]] modules. \\ | * [[https://github.com/analogdevicesinc/hdl/blob/master/library/common/up_axi.v|AXI control and status]] modules. \\ |
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| ==== Device (AD9361) Interface Description ==== | ==== Device (AD9361) Interface Description ==== |
