Differences

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--- resources:fpga:docs:axi_ad9265 [16 Apr 2019 10:27] – [Register Map] Laszlo Nagy
+++ resources:fpga:docs:axi_ad9265 [23 Jan 2020 17:55] – Update DEVICE_TYPE Istvan Csomortani
@@ Line 19: / Line 19: @@
 ^ Name ^ Description ^ Default Value^
 | ''ID'' | Core ID should be unique for each AD9265 IP in the system | 0 |
-| ''DEVICE_TYPE'' | Used to select between Virtex 6 (1) or 7 Series (0) devices  | 0 |
+| ''DEVICE_TYPE'' | Used to select between 7 Series (1), Ultrascale (2) or Ultrascale+ (3) devices  | 0 |
 | ''ADC_DATAPATH_DISABLE'' | If set, the datapath processing is not generated and output data is taken directly from the AD9265  | 0 |
 | ''IO_DELAY_GROUP'' | The delay group name which is set for the delay controller  | "adc_if_delay_group" |
@@ Line 71: / Line 71: @@
 ==== Register Map ====
-==== Register Map base addresses ====
-|< 100% 5% 5% 5% 25% 5% 55% >|
-|Address ||Name |||Description |
-|DWORD |BYTE |::: |::: |::: |::: |
-^0x0000 ^0x0000 ^BASE ^^^See the [[#base_common_to_all_cores|Base (common to all cores)]] table for more detail ^
-^0x0010 ^0x0040 ^RX COMMON ^^^ See the [[#adc_common_axi_ad|ADC Common]] table for more detail ^
-^0x0100 ^0x0400 ^RX CHANNELS ^^^ See the [[#adc_channel_axi_ad|ADC Channel]] table for more detail ^

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