This version is outdated by a newer approved version.
This version (10 Jan 2018 13:27) was approved by Adrian Costina.The Previously approved version (31 Aug 2017 16:56) is available.
This version (10 Jan 2018 13:27) was approved by Adrian Costina.The Previously approved version (31 Aug 2017 16:56) is available.This is an old revision of the document!
Table of Contents
HDL Architecture
Every HDL design of a reference project can be divided into two subsystems:
- The base design, which contains an embedded processor - soft or hard - and all the peripheral IPs that the carrier board supports and are necessary to run a Linux distribution on the system. These designs are carrier dependent, each prototyping board having its own base design.
- The board design, which is a direct integration of all the necessary IP's into a specific base design in order to support an FMC I/O board. These designs are carrier independent and common to all carrier boards.
Currently ADI provides base designs for the following prototyping boards:
| Altera | Xilinx |
|---|---|
| A5SoC | AC701 |
| A5GT | KC705 |
| A10SOC | KCU105 |
| A10GX | VC707 |
| C5SOC | ZC702 |
| ZC706 | |
| ZCU102 | |
| Zedboard | |
| Mini-ITX | |
| Microzed | |
| PicoZed SDR SOM |
Base Design
The base design contains all the I/O peripheral and memory interfaces and processing components, which are necessary for a fully functional Linux system. The majority of these components are Altera and Xilinx IP cores, the details of which are beyond the scope of this document. However, an overview may be worth reading about.
Microprocessor
| Altera | Xilinx | ||
|---|---|---|---|
| SoC | FPGA | SoC | FPGA |
| HPS | NIOS II | PS7 | MicroBlaze™ |
Worth mentioning in case of SoCs, the Hard Processor System (HSP) or Processing System 7 (PS7) do not contains just the dual-core ARM® Cortex® - A9 MPCore™ processor, they also have other integrated peripherals and memory interfaces. For more information please visit the manufacturer's website, listed in the table above.
Memory Interface Controller
In almost all cases, the carrier board is not made and designed by Analog Devices, so the external memory solution of the system is given. Meaning we can not support, modify or alter this important part of the system, in several cases we even have system limitations because of it (e.g. the memory interface is not fast enough to handle the required data throughput).
Under the two links below the user can find the landing page of the available memory solutions for both Altera and Xilinx:
- Altera's memory interfaces: https://www.altera.com/products/intellectual-property/best-in-class-ip/external-memory.html
- Xilinx's memory interfaces: https://www.xilinx.com/products/intellectual-property/mig.html#documentation
Peripheral Interfaces
These interfaces are used to control external peripherals located on the prototyping board or the FMC IO board.
SPI
In general, the base system has two Serial Peripheral Interfaces, which are used as a control interface for FMC/HSMC devices. These SPI interfaces are controlled by the integrated SPI controller of the Hard Processor System (HSP) or Processing System 7 (PS7) or an Altera or Xilinx SPI controller core.
I2C/I2S/SPDIF
A couple of carrier boards require these standard interfaces for different purposes, for example, a configuration interface for an audio peripheral device. These peripherals do not necessarily have vital roles in the reference design, it's more like a generic goal to support all the provided peripherals of the carrier board.
HDMI
There is HDMI support for all the carriers which are using the ADV7511 as HDMI transmitter. The HDMI transmitter core can be found here.
GPIOs
The general rule of thumb is to define 64 GPIO pins for the base design. The 32 LSB bit will be assigned to switches, buttons and/or LEDs, which can be found on the carrier board. The 32 MSB bits can be used for the FMC board.
Connectivity
- Ethernet
- USB OTG
These interfaces designs are borrowed from the golden reference design of the board.
Location of the base design in the design framework
resources/fpga/docs/arch.1515587249.txt.gz · Last modified: 10 Jan 2018 13:27 by Adrian Costina