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| Both sides previous revisionPrevious revision | Last revisionBoth sides next revision | ||
| resources:fpga:altera:ced1z:adas3022 [18 Dec 2015 23:04] – [Quick Evaluation] Ivano Pelicella | resources:fpga:altera:ced1z:adas3022 [07 May 2018 14:09] – Removed testbench from the HDL folder description, as it's not available Adrian Costina | ||
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| | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | ||
| | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script // | | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script // | ||
| - | | Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. | + | | Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. | |
| | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | ||
| | Software | Contains the source files of the Nios2 SBT evaluation project | | | Software | Contains the source files of the Nios2 SBT evaluation project | | ||
resources/fpga/altera/ced1z/adas3022.txt · Last modified: 11 Jan 2021 09:40 by Ioana Chelaru