Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:fpga:altera:ced1z:adas3022 [18 Dec 2015 23:04] – [Quick Evaluation] Ivano Pelicellaresources:fpga:altera:ced1z:adas3022 [11 Jan 2021 09:40] (current) – Fixed bad link for EVAL-ADAS3022 Ioana Chelaru
Line 3: Line 3:
 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>ADAS3022EDZ| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-ADAS3022EDZ Evaluation Board with the CED1 board.+This document presents the steps to setup an environment for using the **[[adi>EVAL-ADAS3022| EVAL-ADAS3022EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-ADAS3022EDZ Evaluation Board with the CED1 board.
  
 {{ :resources:fpga:altera:ced1z:ced1z_adas3022.png?500 }} {{ :resources:fpga:altera:ced1z:ced1z_adas3022.png?500 }}
Line 47: Line 47:
 | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module | | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-ADAS302xEDZ board. The ADAS3022.v file contains the main ADC driver module |
 | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the ADAS3022 registers in ///hdl/src/inc//  | | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the ADAS3022 registers in ///hdl/src/inc//  |
-| Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |+| Hdl | Contains the source files for the ADAS3022 core : \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. |
 | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the ADAS3022 SOPC component |
 | Software | Contains the source files of the Nios2 SBT evaluation project | | Software | Contains the source files of the Nios2 SBT evaluation project |
resources/fpga/altera/ced1z/adas3022.txt · Last modified: 11 Jan 2021 09:40 by Ioana Chelaru

Page Tools