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resources:fpga:altera:ced1z:ad7938 [28 Nov 2011 14:02] – corections Andrei Cozmaresources:fpga:altera:ced1z:ad7938 [26 Jan 2021 01:23] (current) – update arrow links after their web site update Robin Getz
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 ====== CED1Z FPGA Project for AD7938 with Nios driver  ====== ====== CED1Z FPGA Project for AD7938 with Nios driver  ======
  
-====== Overview ======+====== Overview =====
  
-This document presents the steps to setup an environment for using the **[[adi>AD7938|EVAL-AD7938CBZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7938 Evaluation Board with the CED1 board.+This document presents the steps to setup an environment for using the **[[adi>AD7938|EVAL-AD7938CBZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS) and the [[https://www.micrium.com/ucprobe/about/|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7938 Evaluation Board with the CED1 board.
  
 {{ :resources:fpga:altera:ced1z:img_0024.png?500 }} {{ :resources:fpga:altera:ced1z:img_0024.png?500 }}
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 The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link. The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.
  
-The [[adi>AD7938]] is a 12-bit high speed, low power, successive approximation (SAR) analog-to-digital converter (ADC). The part operates from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz. The AD7938 features eight analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. The part can operatewith either single-ended, fully differential, or pseudodifferential analog inputs. The conversion process and data acquisition are controlled using standard control inputs that allow easy interfacing with microprocessors and DSPs. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point. The AD7938 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference. This part use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.+The [[adi>AD7938]] is a 12-bit high speed, low power, successive approximation (SAR) analog-to-digital converter (ADC). The part operates from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz. The AD7938 features eight analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. The part can operatewith either single-ended, fully differential, or pseudodifferential analog inputs. The conversion process and data acquisition are controlled using standard control inputs that allow easy interfacing with microprocessors and DSPs. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point. The AD7938 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference. This part uses advanced design techniques to achieve very low power dissipation at high throughput rates. It also features flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.
  
-The **EVAL-AD7671CBZ** is a fully featured evaluation kit for the AD7938. This board operates in stand alone mode or in conjunction with the Converter Evaluation and Development board, EVAL-CED1Z . When operated with the Converter Evaluation and Development board, software is provided enabling the user to perform detailed analysis of the ADC's performance.+The **EVAL-AD7938CBZ** is a fully featured evaluation kit for the AD7938. This board operates in stand alone mode or in conjunction with the Converter Evaluation and Development board, EVAL-CED1Z . When operated with the Converter Evaluation and Development board, software is provided enabling the user to perform detailed analysis of the ADC's performance.
  
 ===== More information ===== ===== More information =====
  
   * [[adi>AD7938|AD7938 Product Info]] - pricing, samples, datasheet   * [[adi>AD7938|AD7938 Product Info]] - pricing, samples, datasheet
-  * [[adi>/static/imported-files/eval_boards/17099365EVAL_AD7938CB_AD7939CB_AD7938_6CB.pdf|EVAL-AD7939CBZ evaluation board user guide]]+  * [[adi>/static/imported-files/eval_boards/17099365EVAL_AD7938CB_AD7939CB_AD7938_6CB.pdf|EVAL-AD7938CBZ evaluation board user guide]]
   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+  * [[https://www.micrium.com/ucprobe/about/|Micrium uC-Probe v2.5]]
  
 ====== Getting Started ====== ====== Getting Started ======
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   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool +  * [[https://www.micrium.com/ucprobe/about/|uC-Probe v2.5]] run-time monitoring tool 
-  * {{:resources:fpga:altera:ced1z:ad7671_evalboard.zip|Evaluation Project Files}} + 
 The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.  The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 
  
 The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. **Note:** After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. **Note:** After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list.
  
 +===== Downloads =====
 +  * {{:resources:fpga:altera:ced1z:ad7938_evalboard.zip|Evaluation Project Files}}   
 ===== Extract the Lab Files ===== ===== Extract the Lab Files =====
  
-Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7938_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Software//**, **//ucProbeInterface//**, **//NiosCpu//**, **//QuickEvaluation//**.+Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7938_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//ucProbe//**.
  
 +^ **Folder** ^ **Description** ^
 +| FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA with be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL drivers in ///hdl/src// , the software drivers for HAL in ///hdl/src/HAL// and the AD7938 registers in ///hdl/src/inc// . |
 +| Hdl | Contains the source files for the AD7938 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the driver. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the driver's testbench. |
 +| NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7938 SOPC component. |
 +| Software | Contains the source files of the uCProbe library and the main file of the Nios2 SBT evaluation project.|
 +| uCProbe | Contains the uCProbe interface and data capture script used to acquire data from the evaluation board and store it in a local .csv file. |
 ===== Install the USB-Blaster Device Driver ===== ===== Install the USB-Blaster Device Driver =====
- +{{page>:resources:fpga:altera:ced1z:common_usb}}
-The USB Blaster is used to program the FPGA on the CED1Z board and also for data exchange between the system and a PC. To install the driver plug the Terasic USB Blaster into one of the PCs USB ports. Your Windows PC will find the new hardware and try to install the driver. +
- +
-{{ :resources:fpga:altera:bemicro:image007.png?350 }} +
- +
-Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the //Device Manager// right click on the **USB-Blaster** device and select **//Update Driver Software//**. +
- +
-{{ :resources:fpga:altera:bemicro:image009.png?700 }} +
- +
-In the next dialog box select the option **//Browse my computer for driver software//**. A new dialog will open where it is possible to point to the driver’s location. Set the location to **altera\11.0\quartus\drivers\usb-blaster** and press **//Next//**. +
- +
-{{:resources:fpga:altera:bemicro:image011.png?400}}{{:resources:fpga:altera:bemicro:image013.png?400}} +
-<WRAP clear></WRAP> +
-<note tip>If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “**//Install this driver software anyway//**”. Upon installation completion a message will be displayed to inform that the installation is finished.</note> +
- +
-{{:resources:fpga:altera:bemicro:image017.png?400}}{{:resources:fpga:altera:bemicro:image016.jpg?400}}+
  
 ======= AD7938 Evaluation Project Overview ======= ======= AD7938 Evaluation Project Overview =======
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 ^ Name ^ Offset ^ Width ^ Access ^ Description ^ ^ Name ^ Offset ^ Width ^ Access ^ Description ^
-| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location \\ Bit 3 is used to write data to the AD7671 evaluation board|+| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location \\ Bit 3 is used to write data to the AD7938 evaluation board|
 | ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started | | ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started |
 | BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written | | BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written |
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 ======== Quick Evaluation ======== ======== Quick Evaluation ========
 +{{page>:resources:fpga:altera:ced1z:common_quick_evaluation}}
  
-The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system that can be used together with the uC-Probe interface for the ADI platform evalution. +====== NIOS II Software Design ======
-The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the **Quartus II Web Edition** tool or the [[https://www.altera.com/download/programming/quartus2/pq2-index.jsp|Quartus II Programmer]] must be installed on your computer. +
-To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. If so, connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the **//quick_evaluation.bat//** batch file located in the **//ADIEvalBoard/QuickEvaluation//** folder. +
-Now the FPGA contains a fully functional system and it is possible to skip directly to the **Evaluation Project User Interface** section of this document.+
  
- 
-====== NIOS II Software Design ====== 
  
 This section presents the steps for developing a software application that will run on the **CED1Z** system and will be used for controlling and monitoring the operation of the ADI evaluation board. This section presents the steps for developing a software application that will run on the **CED1Z** system and will be used for controlling and monitoring the operation of the ADI evaluation board.
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 Launch the **Nios II SBT** from the **//Start -> All Programs -> Altera -> Nios II EDS 11.0 -> Nios II 11.0 Launch the **Nios II SBT** from the **//Start -> All Programs -> Altera -> Nios II EDS 11.0 -> Nios II 11.0
 Software Build Tools for Eclipse (SBT)//**. Software Build Tools for Eclipse (SBT)//**.
-<note tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</note>+<WRAP tip>NOTE: Windows 7 users will need to right-click and select **//Run as administrator//**. Another method is to right-click and select **//Properties//** and click on the //**Compatibility**// tab and select the **//Run This Program As An Administrator//** checkbox, which will make this a permanent change.</WRAP>
  
 === 1. Initialize Eclipse workspace === === 1. Initialize Eclipse workspace ===
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   * Click the **//Finish//** button.   * Click the **//Finish//** button.
  
-{{ :resources:fpga:altera:bemicro:eclipseblankproject.png?600 }}+{{ :resources:fpga:altera:ced1z:eclipseblankproject.png?600 }}
  
 The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace. The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.
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 The memory used by the design is should be changed from OnChip ram to SRAM. The memory used by the design is should be changed from OnChip ram to SRAM.
   * Select **//Linker Script//** tab.   * Select **//Linker Script//** tab.
-  * Change all possible **//Linker region name//** from **//onchip_mem//** to **//SRAM//**.+  * Change all possible **//Linker Region Name//** from **//onchip_mem//** to **//sram//**.
  
-{{ :resources:fpga:altera:cedz:cedzsinkersettings.png?800 }}+{{ :resources:fpga:altera:ced1z:ced1zlinkersettings8bit.png?800 }}
  
   * Select **//File -> Save//** to save the board support package configuration to the //settings.bsp// file.   * Select **//File -> Save//** to save the board support package configuration to the //settings.bsp// file.
   * Click the **//Generate//** button to update the BSP.   * Click the **//Generate//** button to update the BSP.
   * When the generate has completed, select **//File -> Exit//** to close the BSP Editor.   * When the generate has completed, select **//File -> Exit//** to close the BSP Editor.
- 
-===== Configure BSP Project Build Properties ===== 
- 
-In addition to the board support package settings configured using the **//BSP Editor//**, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level. 
-  * Right click on the **//ADIEvalBoard_bsp//** software project and select **//Properties//** from the right-click menu. 
-  * On the left-hand menu, select **//Nios II BSP Properties//**. 
-  * During compilation, the code may have various levels of optimization which is a tradeoff between code size and performance. Change the **//Optimization level//** setting to **//Level 2//** 
-  * Since our software does not make use of C++, uncheck **//Support C++//**. 
-  * Check the **//Reduced device drivers//** option 
-  * Check the **//Small C library//** option 
-  * Press **//Apply//** and **//OK//** to regenerate the BSP and close the **//Properties//** window. 
- 
-{{ :resources:fpga:altera:bemicro:eclipsebspproperties.png?500 }} 
  
 ===== Add source code to the project ===== ===== Add source code to the project =====
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 {{ :resources:fpga:altera:ced1z:eclipseprojectfiles.png }} {{ :resources:fpga:altera:ced1z:eclipseprojectfiles.png }}
- 
-===== Configure Application Project Build Properties ===== 
- 
-Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project **//ADIEvalBoard//** as well. 
-  * Right click on the **//ADIEvalBoard//** software project and select **//Properties//** from the right-click menu. 
-  * On the left-hand menu, select the **//Nios II Application Properties//** tab 
-  * Change the **//Optimization level//** setting to **//Level 2//**. 
-  * Press **//Apply//** and **//OK//** to save the changes. 
- 
-{{ :resources:fpga:altera:bemicro:eclipseprojproperties.png?600 }} 
  
 ===== Define Application Include Directories ===== ===== Define Application Include Directories =====
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 To run the software project on the Nios II processor: To run the software project on the Nios II processor:
  
-  * Press the **//Run//** button in the **//Run Configurations//** window. +   * Before running the the software project, the FPGA located on the CED1Z must be programmed with the Nios II system image. To program the FPGA run the //**ADIEvalBoard/FPGA/program_fpga.bat**// script. 
- +   * Press the **//Run//** button in the **//Run Configurations//** window. This will re-build the software project to create an up–to-date executable and then download the code into memory on the **CED1Z** hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed
-This will re-build the software project to create an up–to-date executable and then download the code into memory on the **CED1Z** hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed.+
  
 {{ :resources:fpga:altera:cedz:image063.png?500 }} {{ :resources:fpga:altera:cedz:image063.png?500 }}
  
-<note>The code size and start address might be different than the ones displayed in the above screenshot.</note>+<WRAP round help>The code size and start address might be different than the ones displayed in the above screenshot.</WRAP>
  
-====== Evaluation Project User Interface ====== 
  
-The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD7671CBZ evaluation board. +====== uC-Probe Interface ====== 
 +{{page>:resources:fpga:altera:ced1z:common_ucprobe}}
  
-{{ :resources:fpga:altera:cedz:ucprobe_interface.png?600 |Demonstration Project User Interface}}+===== Load and Run the Demonstration Project =====
  
-The TCL script window will look something like the following:+  * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ADIEvalBoard/ucProbe/AD7938_Interface.wsp//**.
  
-{{ :resources:fpga:altera:cedz:cmd_interface.png?600 |Demonstration Project Command Interface}}+{{:resources:fpga:altera:ced1z:ucprobeopen.png?400}}{{:resources:fpga:altera:ced1z:ad7938interfaceopen.png?400}}
  
-The following steps must be performed in order to acquire the data from ADC: +  * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoard/ucProbe/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoard/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file.
-  - Make sure the CED1Z Windows driver is not active when connecting the USB cable to the CED1Z. +
-  - Connect an USB blaster to the CED1Z board. +
-  - The next three steps are performed by the quick_evaluation.bat batch file. They can be performed manually if desired. +
-    - Program the Cyclone FPGA. +
-    - Download the Nios2 Application. +
-    - Start the **//data_capture.bat//** batch. +
-  - Start **//uc/Probe//** application. +
-  - Depending on how the AD7938 part is configured select either Binary Offset or 2's Complement.  +
-  - Press **//Acquisition//** button. At this point 1 Mbyte of data will be acquired from the ADC. The data will be saved in a CSV file in rows of 512 samples. +
-  - The **//Acquisition In Progress//** LED will be lit as long as data is acquired from the acquisition board. +
-  - The **//Transfer In Progress//** LED will be lit as long as data is transfered from the CED1Z system to the PC. +
-  - The **//Processing Data In Progress//** LED will be lit as long as the data will be converted to either Binary offset or 2's Complement 16 bit values. +
-  - The **//Writing File In Progress//** LED will be lit as long as data is added to **//Acquisition.csv//** file, in the same directory with the AD7671.bat. +
-  - After the acquisition is complete the data will be available in the **//Acquisition.csv//** file.  +
-  - You can start a new acquisition by reactivating the **//Acquisition//** button.  +
-  - After all the needed data is acquired, close the uCProbe program and the cmd window. +
-If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. +
-====== Troubleshooting ======+
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +{{:resources:fpga:altera:ced1z:loadelfucprobe.png?400}}{{:resources:fpga:altera:ced1z:loadelfsoftware.png?400}}
-  * Check that the evaluation board is powered. +
-  * Make sure the USB cable is not connected to the CED1Z. In case it is, disconnect it and reset the board. +
-  * Check that the USB Blaster cable is properly connected to the device and to the computer and that the **//USB Blaster Device Driver//** driver is installed correctly. If the deriver is not correctly installed perform the steps described in the **//Getting Started -> Install te USB-Blaster Device Driver//** section. +
-  * In uC-Probe right-click on the **//System Browser//** window select **//Remove Symbols//**. A dialog box will open to select the symbols to remove. Press OK to remove the symbols.+
  
-{{:resources:fpga:altera:bemicro:ucproberemovesymbols.png?400}}{{:resources:fpga:altera:bemicro:ucproberemovesymbolsdlg.png?400}}+  * Run the demonstration project by pressing the **//Play//** button.
  
-  * After removing the symbols a new set of symbols must be added in order for the interface to be functional. In uC-Probe right-click on the **//System Browser//** window select **//Add Symbols//**. A dialog box will open to select the symbols to be added. If the lab was done according to the steps provided in the Quick Evaluation section, select the file **//ADIEvalBoard/ucProbeInterface/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoard/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file.+{{ :resources:fpga:altera:bemicro:image081.png?300 }}
  
-{{ :resources:fpga:altera:bemicro:ucprobeaddsymbols.png?400 }}+  * Run the //**ADIEvalBoard/uCProbe/data_capture.bat**// script. A DOS command prompt window will open. This window must be closed only when the uCProbe demonstration project will be closed. 
 +====== Evaluation Project User Interface ======
  
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD7938CBZ evaluation board.  
 + 
 +{{ :resources:fpga:altera:ced1z:ucprobe_interface.png?600 |Demonstration Project User Interface}} 
 + 
 +In order to capture data from the ADC using the uCProbe demonstration project the following steps must be performed: 
 +  * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board. 
 +  * Start **//uc/Probe//** application. 
 +  * Depending on how the AD7938 part is configured set the data format to either //**Binary Offset**// or //**2's Complement**//.  
 +  * Set the states of the bits from the //**Control**// and //**Shadow**// registers. 
 +  * Press **//Acquisition//** button. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The **//Acquisition In Progress//** LED is lit to signal that the data is acquired from the ADC. When the data acquisition is complete the //**Acquisition Complete**// LED turns green. 
 +  * The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. The **//Transfer In Progress//** LED is lit as long as the data is transferred from the CED1Z to the PC. Whe the data transfer is complete the //**Transfer Complete**// LED turns green. 
 +  * After the data is transferred to the PC it is converted to either Binary offset or 2's Complement 16 bit values. The **//Processing Data In Progress//** LED is lit as long as the data conversion is performed. When the conversion is complete the //**Processing Data Complete**// LED turns green.  
 +  * The data captured from the ADC is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. While the data is saved the **//Writing File In Progress//** LED is lit. When the data write process is complete the //**Writing in File Complete**// LED turns green. 
 +  * The data capture status is also displayed in the opened command window as shown in the figure below. 
 + 
 +{{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}} 
 + 
 +  * A new acquisition can be started by reactivating the **//Acquisition//** button.  
 +  * After all the needed data is acquired the uCProbe program and the command window can be closed. 
 + 
 +//**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. 
 +====== Troubleshooting ====== 
 +{{page>:resources:fpga:altera:ced1z:common_troubleshooting}}
  
resources/fpga/altera/ced1z/ad7938.1322485340.txt.gz · Last modified: 28 Nov 2011 14:02 by Andrei Cozma

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