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resources:fpga:altera:ced1z:ad7766 [21 Aug 2012 16:08] – Changed acquisition procedure to use only scripts Adrian Costinaresources:fpga:altera:ced1z:ad7766 [11 Jan 2021 09:38] (current) – Fixed bad links for AD7766 Ioana Chelaru
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 ===== Supported Devices ===== ===== Supported Devices =====
  
-  * [[adi>AD7766-1]]+  * [[adi>AD7766|AD7766-1]]
  
 ===== Evaluation Boards ===== ===== Evaluation Boards =====
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD7766-1|EVAL-AD7766-1EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7766-1 Evaluation Board with the CED1 board.+This document presents the steps to setup an environment for using the **[[adi>EVAL-AD7766-1EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7766-1 Evaluation Board with the CED1 board.
  
 {{ :resources:fpga:altera:ced1z:ced1z_ad7766.png?500 }} {{ :resources:fpga:altera:ced1z:ced1z_ad7766.png?500 }}
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 The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link. The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.
  
-The [[adi>AD7766| AD7766-1]] is a high performance 24-bit oversampled SAR analog-to-digital converter (ADC). TheAD7766-1 combines the benefits of a large dynamic range and input bandwidth, consuming  10.5 mW power,  contained in a 16-lead TSSOP package.+The [[adi>AD7766| AD7766-1]] is a high performance 24-bit oversampled SAR analog-to-digital converter (ADC). The AD7766-1 combines the benefits of a large dynamic range and input bandwidth, consuming  10.5 mW power,  contained in a 16-lead TSSOP package.
  
 ===== More information ===== ===== More information =====
  
-  * [[adi>AD7766-1|AD7766-1 Product Info]] - pricing, samples, datasheet+  * [[adi>AD7766|AD7766-1 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/eval_boards/EVAL-AD7766_7766-1_7766-2EDZ_PrB.pdf|EVAL-AD7766-1EDZ evaluation board user guide]]   * [[adi>/static/imported-files/eval_boards/EVAL-AD7766_7766-1_7766-2EDZ_PrB.pdf|EVAL-AD7766-1EDZ evaluation board user guide]]
   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
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   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0   * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0   * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0
-  * {{:resources:fpga:altera:ced1z:ad7766_evalboard.zip|Evaluation Project Files}} 
  
 The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.  The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. 
 +
 +===== Downloads =====
 +  * {{:resources:fpga:altera:ced1z:ad7766_evalboard.zip|Evaluation Project Files}}
  
  
resources/fpga/altera/ced1z/ad7766.1345558085.txt.gz · Last modified: 21 Aug 2012 16:08 by Adrian Costina

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