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| resources:fpga:altera:ced1z:ad7766 [25 May 2012 12:57] – created Adrian Costina | resources:fpga:altera:ced1z:ad7766 [05 Nov 2012 21:20] – [Software Tools] Andrei Cozma |
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| ====== Overview ====== | ====== Overview ====== |
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| This document presents the steps to setup an environment for using the **[[adi>AD7766-1|EVAL-AD7766-1EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]**, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7766-1 Evaluation Board with the CED1 board. | This document presents the steps to setup an environment for using the **[[adi>AD7766-1|EVAL-AD7766-1EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7766-1 Evaluation Board with the CED1 board. |
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| {{ :resources:fpga:altera:ced1z:ced1z_ad7766.png?500 }} | {{ :resources:fpga:altera:ced1z:ced1z_ad7766.png?500 }} |
| * [[adi>/static/imported-files/eval_boards/EVAL-AD7766_7766-1_7766-2EDZ_PrB.pdf|EVAL-AD7766-1EDZ evaluation board user guide]] | * [[adi>/static/imported-files/eval_boards/EVAL-AD7766_7766-1_7766-2EDZ_PrB.pdf|EVAL-AD7766-1EDZ evaluation board user guide]] |
| * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]] | * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]] |
| * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] | |
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| ====== Getting Started ====== | ====== Getting Started ====== |
| * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 | * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0 |
| * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 | * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0 |
| * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool | |
| * {{:resources:fpga:altera:ced1z:ad7766_evalboard.zip|Evaluation Project Files}} | |
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| The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. |
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| The **Micrium uC/Probe Trial** version is available via download from the web at [[http://micrium.com/download/Micrium-uC-Probe-Setup-Trial.exe]]. **Note:** After installation add to the “Path” system variable the entry "//%QUARTUS_ROOTDIR%\bin\//“ on the third position in the list. | ===== Downloads ===== |
| | * {{:resources:fpga:altera:ced1z:ad7766_evalboard.zip|Evaluation Project Files}} |
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| ===== Extract the Lab Files ===== | ===== Extract the Lab Files ===== |
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| Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7766_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//ucProbe//** | Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7766_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//**, **//DataCapture//** |
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| ^ **Folder** ^ **Description** ^ | ^ **Folder** ^ **Description** ^ |
| | Hdl | Contains the source files for the AD7766 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. \\ - The //tb// folder contains the sources of the core's testbench | | | Hdl | Contains the source files for the AD7766 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. \\ - The //tb// folder contains the sources of the core's testbench | |
| | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7766 QSYS component | | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7766 QSYS component | |
| | Software | Contains the source files of the uCProbe library and the main file of the Nios2 SBT evaluation project | | | Software | Contains the source files of the Nios2 SBT evaluation project | |
| | uCProbe | Contains the uCProbe interface and data capture script used to acquire data from the evaluation board and store it in a local .csv file | | | DataCapture | Contains the script files used for data acquisition | |
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| ===== Install the USB-Blaster Device Driver ===== | ===== Install the USB-Blaster Device Driver ===== |
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| ====== Quick Evaluation ====== | ====== Quick Evaluation ====== |
| {{page>:resources:fpga:altera:ced1z:common_quick_evaluation}} | {{page>:resources:fpga:altera:ced1z:quick_evaluation}} |
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| ====== NIOS II Software Design ====== | ====== NIOS II Software Design ====== |
| {{page>:resources:fpga:altera:ced1z:common_nios2_software_design}} | {{page>:resources:fpga:altera:ced1z:common_software_design}} |
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| ====== uC-Probe Interface ====== | |
| {{page>:resources:fpga:altera:ced1z:common_ucprobe}} | |
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| ===== Load and Run the Demonstration Project ===== | |
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| * Click the **//Open//** option from the **uC-Probe** menu and select the file **//ADIEvalBoard/ucProbe/AD7766_Interface.wsp//**. | |
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| {{:resources:fpga:altera:ced1z:ucprobeopen.png?400}}{{:resources:fpga:altera:ced1z:ad7766interfaceopen.png?400}} | |
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| * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the **Quick Evaluation** section, select the file **//ADIEvalBoard/ucProbe/ADIEvalBoard.elf//** to be loaded as a symbol file, otherwise select the file **//ADIEvalBoard/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf//** to be loaded as a symbol file. | |
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| {{:resources:fpga:altera:ced1z:loadelfucprobe.png?400}}{{:resources:fpga:altera:ced1z:loadelfsoftware.png?400}} | |
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| * Run the demonstration project by pressing the **//Play//** button. | |
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| {{ :resources:fpga:altera:bemicro:image081.png?300 }} | |
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| * Run the //**ADIEvalBoard/uCProbe/data_capture.bat**// script. A DOS command prompt window will open. This window must be closed only when the uCProbe demonstration project will be closed. | |
| ====== Evaluation Project User Interface ====== | ====== Evaluation Project User Interface ====== |
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| The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD7766-1EDZ evaluation board. | In order to capture data from the ADC the following steps must be performed: |
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| {{ :resources:fpga:altera:ced1z:ad7766interface.png?600 |Demonstration Project User Interface}} | |
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| In order to capture data from the ADC using the uCProbe demonstration project the following steps must be performed: | |
| * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board. | * Make sure that the //**CED1Z FPGA**// is properly programmed and the USB Blaster is connected to the CED1Z board. |
| * Start **//uc/Probe//** application. | * Execute //**data_capture.bat**// script. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. After the data is transferred to the PC it is converted to 2's Complement 24 bit values. |
| * Press **//Activate//** button. At this point 1 Mbyte of data will be acquired from the ADC and saved into the CED1Z SRAM memory. The **//Acquisition In Progress//** LED is lit to signal that the data is acquired from the ADC. When the data acquisition is complete the //**Acquisition Complete**// LED turns green. | * The resulting data is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. |
| * The data stored in the CED1Z SRAM memory is transfered to the PC through the JTAG-UART link provided by the USB Blaster. The **//Transfer In Progress//** LED is lit as long as the data is transferred from the CED1Z to the PC. Whe the data transfer is complete the //**Transfer Complete**// LED turns green. | |
| * After the data is transferred to the PC it is converted to 2's Complement 24 bit values. The **//Processing Data In Progress//** LED is lit as long as the data conversion is performed. When the conversion is complete the //**Processing Data Complete**// LED turns green. | |
| * The data captured from the ADC is saved into a comma separated values (.csv) file named **//Acquisition.csv//**, located in the same folder as the //**data_capture.bat**// file. While the data is saved the **//Writing File In Progress//** LED is lit. When the data write process is complete the //**Writing in File Complete**// LED turns green. | |
| * The data capture status is also displayed in the opened command window as shown in the figure below. | * The data capture status is also displayed in the opened command window as shown in the figure below. |
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| {{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}} | {{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}} |
| * A new acquisition can be started by reactivating the **//Activate//** button. | * A new acquisition can be started by executing the //**data_capture.bat**// script. |
| * After all the needed data is acquired the uCProbe program and the command window can be closed. | |
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| //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. | //**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file. |
| //**Note:**// If the design's clock settings have been changed, it may happen that the internal FIFO memory buffer is overflown. The **//FIFO Overflow//** LED will be lit. In that case, data acquired may be invalid. In order to retrieve new data, press **//Reset Core//** button before a new acquisition. | |
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| ====== Troubleshooting ====== | |
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| {{page>:resources:fpga:altera:ced1z:common_troubleshooting}} | ====== More information ====== |
| | * [[ez>community/fpga|ask questions about the FPGA reference design]] |
| | * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}} |
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