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resources:fpga:altera:ced1z:ad7699 [25 Mar 2013 14:19] – created Istvan Csomortani | resources:fpga:altera:ced1z:ad7699 [25 Mar 2013 15:10] (current) – [Evaluation Project Data Acquisition] Istvan Csomortani | ||
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+ | ====== CED1Z FPGA Project for AD7699 with Nios driver | ||
+ | |||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[adi> | ||
+ | |||
+ | ===== Evaluation Boards ===== | ||
+ | |||
+ | * [[adi> | ||
+ | |||
+ | ====== Overview ====== | ||
+ | |||
+ | This document presents the steps to setup an environment for using the **[[adi> | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link. | ||
+ | |||
+ | The [[adi> | ||
+ | The AD7699 contains all components for use in a multichannel, | ||
+ | |||
+ | ===== More information ===== | ||
+ | |||
+ | * [[adi> | ||
+ | * [[adi>/ | ||
+ | * [[http:// | ||
+ | |||
+ | ====== Getting Started ====== | ||
+ | |||
+ | The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project. | ||
+ | |||
+ | ===== Hardware Items ===== | ||
+ | |||
+ | Below is presented the list of required hardware items: | ||
+ | * Analog Devices [[adi> | ||
+ | * [[http:// | ||
+ | * **EVAL-AD7699EDZ** evaluation board | ||
+ | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | ||
+ | |||
+ | ===== Software Tools ===== | ||
+ | |||
+ | Below is presented the list of required software tools: | ||
+ | * [[http:// | ||
+ | * [[https:// | ||
+ | |||
+ | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | ||
+ | |||
+ | ===== Downloads ===== | ||
+ | |||
+ | * {{: | ||
+ | |||
+ | |||
+ | ===== Extract the Lab Files ===== | ||
+ | |||
+ | Create a folder called “**// | ||
+ | ^ **Folder** ^ **Description** ^ | ||
+ | | EvalBoardFPGA | Contains the reference project which is loaded on the EVAL-AD689EDZ board. The AD7699.v file contains the main ADC driver modules | | ||
+ | | FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script // | ||
+ | | Hdl | Contains the source files for the AD7699 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files. | ||
+ | | NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7699 QSYS component | | ||
+ | | Software | Contains the source files of the Nios2 SBT evaluation project | | ||
+ | | DataCapture | Contains the script files used for data acquisition | | ||
+ | |||
+ | ===== Install the USB-Blaster Device Driver ===== | ||
+ | |||
+ | {{page>: | ||
+ | |||
+ | ======= AD7699 Evaluation Project Overview ======= | ||
+ | |||
+ | The evaluation project contains all the source files needed to build a system that can be used to configure the AD7699 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis. | ||
+ | |||
+ | ===== CED1Z FPGA Design ===== | ||
+ | |||
+ | The following components are implemented in the FPGA design: | ||
+ | |||
+ | ^ Name ^ Address | ||
+ | | CPU | 0x00000800 | ||
+ | | PLL | 0x00000000 | ||
+ | | ONCHIP_MEM | ||
+ | | LEDS | 0x00000010 | ||
+ | | SYSID | 0x00000020 | ||
+ | | SRAM | 0x00400000 | ||
+ | | TRISTATE_BRIDGE_0 | ||
+ | | UCPROBE_UART | ||
+ | | JTAG_UART_0 | ||
+ | | SYS_TIMER | ||
+ | | MM_CONSOLE_MASTER | ||
+ | | PWR_DATA | ||
+ | | I2C_INT | ||
+ | | PWR_EN_CLK | ||
+ | | AD7699_0 | ||
+ | | **Table 1 System components** | ||
+ | |||
+ | The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the evaluation board. Following is presented a block diagram of the HDL core and a description of the interface signals. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | Table 2 describes the port definitions of the Avalon peripheral: | ||
+ | |||
+ | ^ Port ^ Direction ^ Width ^ Description ^ | ||
+ | | //**Generic pins**// |||| | ||
+ | | FPGA_CLK_I | ||
+ | | RESET_I | ||
+ | | //**Avalon Slave Interface**// | ||
+ | | AVALON_WRITEDATA_I | ||
+ | | AVALON_WRITE_I | ||
+ | | AVALON_READ_I | ||
+ | | AVALON_ADDRESS_I | ||
+ | | AVALON_READDATA_O | ||
+ | | //**Avalon Master Interface**// | ||
+ | | AVALON_MASTER_WAITREQUEST | IN | 1 | Master wait request signal | | ||
+ | | AVALON_MASTER_ADDRESS_O | ||
+ | | AVALON_MASTER_WRITE_O | ||
+ | | AVALON_MASTER_BYTEENABLE_O| OUT | 4 | Master byte enable signals | | ||
+ | | AVALON_MASTER_WRITEDATA_O | OUT | 32 | Master write data bus | | ||
+ | | // | ||
+ | | BDB_IO | ||
+ | | BBUSY_I | ||
+ | | BRD_N_O | ||
+ | | BWR_N_O | ||
+ | | BADDR_O | ||
+ | | BRESET_O | ||
+ | | **Table 2 Port description** | ||
+ | |||
+ | Table 3 describes the registers of the Avalon peripheral: | ||
+ | |||
+ | ^ Name ^ Offset ^ Width ^ Access ^ Description ^ | ||
+ | | CONTROL_REGISTER | ||
+ | | ACQ_COUNT_REGISTER | ||
+ | | BASE_REGISTER | ||
+ | | STATUS | ||
+ | | DUT_WRITE_REGISTER | ||
+ | | **Table 3 Register description** | ||
+ | |||
+ | The follwing figure presents the timing diagram for the read operations from the AD7699 driver . | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | ===== AD7699 Evaluation Board Design ===== | ||
+ | |||
+ | In order to acquire data from the AD7699, several modules are implemented in the evaluation board FPGA. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | === AD7699 module === | ||
+ | |||
+ | This module is the actual driver of the AD7699 data acquisition system. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | ^ Port ^ Direction ^ Width ^ Description ^ | ||
+ | | //**General Connectors**// | ||
+ | | FPGA_CLK_I | ||
+ | | ADC_CLK_I | ||
+ | | RESET_I | ||
+ | | // | ||
+ | | WR_DATA_N_I | ||
+ | | DATA_I | ||
+ | | DATA_CHANNELS_O | ||
+ | | DATA_RD_READY_O | ||
+ | | DATA_WR_READY_O | ||
+ | | //**AD7699 connectors**// | ||
+ | | MISO_I | ||
+ | | MOSI_O | ||
+ | | SCLK_O | ||
+ | | CNV_O | OUT | 1 | Signal connected to the CNV pin of the AD7699 | | ||
+ | | **Table 4 Port description for the AD7699 module** | ||
+ | |||
+ | === CED1Z_interface === | ||
+ | |||
+ | This module is used to communicate with the CED1Z board. It reads the data from the AD7699 module and forwards it to the CED1Z board. It also forwards write requests from the CED1Z board to the AD7699 module, in order to reconfigure the AD7699 acquisition system. In case the acquisition is done on 8 channels, data is mapped at addresses starting from 0x10 (channel 0) to 0x17 (channel 8). In case a single channel is acquired, data is mapped sequentially on each of the eight addresses. In this case, data must be concatenated by the module running on the CED1Z board. | ||
+ | |||
+ | === PLL === | ||
+ | |||
+ | This module is used to generate a 40 MHz clock signal from the 100MHz external clock signal that is available on the evaluation board. | ||
+ | |||
+ | ====== Quick Evaluation ====== | ||
+ | |||
+ | The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/ | ||
+ | |||
+ | The Evaluation Board design presented on this page is different than the default design loaded on the AD7699EDZ. In order to use the design from this page, the Evaluation Board FPGA must be reprogrammed. To reprogram the FPGA on the Evaluation board, the following steps must be followed, AFTER the CED1Z FPGA has been programmed using program_fpga.bat: | ||
+ | * 1. Connect the USB-Blaster to the P2 port | ||
+ | * 2. Start Quartus II, Start Tools -> | ||
+ | * 3. Select Mode Active Serial Programming | ||
+ | * 4. Press Add File and select EvalBoardAD7699.pof | ||
+ | * 5. Check Program/ | ||
+ | * 6. After the programming ends, power off the CED1Z and reprogramm it using program_fpga.bat as described above. | ||
+ | |||
+ | <WRAP round help> This is a one time operation, as the programming is done on a non volatile memory on the Evaluation Board. In order to restore the original firmware on the Evaluation Board, at step 4 use the configuration file from the CD at Evaluation Board FPGA code/uMUX FPGA CED 2-2/ | ||
+ | |||
+ | In order to acquire data, follow the instructions in the // | ||
+ | |||
+ | ====== NIOS II Software Design ====== | ||
+ | |||
+ | {{page>: | ||
+ | |||
+ | ====== Evaluation Project Data Acquisition ====== | ||
+ | |||
+ | After the FPGA is correctly programmed the data acquisition process can start by executing the batch script, called **data_capture.bat**. | ||
+ | |||
+ | The script by default collects data from a single channel (channel 0) at 500 KSPS. By editing the **data_catupre.tcl** file, the configuration of the AD7699 can be changed. After changing the tcl script, it is not necessary to reinitialize the system, just rerun the batch script. | ||
+ | |||
+ | If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a single column or on 8 columns in function of the current configuration, | ||
+ | |||
+ | If the AD7699 is configured to acquire less than 8 channels the remaining channels will have a constant value. For example, in the below picture, the AD7699 was configure to acquire data on 4 differential channels, a sine signal was applied on the first channel and the rest were left floating. In this case, the first column can be plotted as a sine wave, the next 3 have some noise on them, and the last 4 have a constant value of 0. | ||
+ | |||
+ | |||
+ | |||
+ | {{ : | ||
+ | |||
+ | ====== More information ====== | ||
+ | * [[ez> | ||
+ | * Example questions: {{rss> | ||