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====== CED1Z FPGA Project for AD7401/01A with Nios driver  ======

===== Supported Devices =====

  * [[adi>AD7401]]
  * [[adi>AD7401A]]

===== Evaluation Boards =====

  * [[adi>EVAL-AD7401EDZ]]
  * [[adi>EVAL-AD7401AEDZ]]


====== Overview ======

This document presents the steps to setup an environment for using the **[[adi>AD7401|EVAL-AD7401EDZ]]** evaluation board together with the **[[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]** and the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7401 Evaluation Board with the CED1 board.

{{ :resources:fpga:altera:ced1z:ced1z_ad7401.png?500 }}

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The [[adi>AD7401| AD7401]] and [[adi>AD7401A |AD7401A]] are second-order, sigma-delta modulators that convert an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. They operate from a 5 V power supply and accept a differential input signal of ±200 mV for AD7401 and ±250 mV for AD7401A (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 20 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2).

===== More information =====

  * [[adi>AD7401|AD7401 Product Info]] - pricing, samples, datasheet
  * [[adi>AD7401A|AD7401A Product Info]] - pricing, samples, datasheet
  * EVAL-AD7401/01AEDZ evaluation board user guide, available when installing the reference software from the CD
  * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]

====== Getting Started ======

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

===== Hardware Items =====

Below is presented the list of required hardware items:
  * Analog Devices [[adi>EVAL-CED|EVAL-CED Converter Evaluation and Development (CED) Board]]
  * [[http://www.terasic.com.tw/|Terasic USB Blaster]]
  * [[adi>EVAL-AD7401EDZ |EVAL-AD7401EDZ evaluation board ]] or 
  * [[adi>EVAL-AD7401AEDZ |EVAL-AD7401AEDZ evaluation board ]]
  * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

===== Software Tools =====

Below is presented the list of required software tools:
  * [[http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html|Quartus II Web Edition]] design software v11.0
  * [[https://www.altera.com/download/software/nios-ii|Nios II EDS]] v11.0

The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web.

===== Downloads =====
  * {{:resources:fpga:altera:ced1z:ad7401_evalboard.zip|Evaluation Project Files}}

===== Extract the Lab Files =====
Create a folder called “**//ADIEvalBoard//**” on your PC and extract the **//ad7401_evalboard.zip//** archive to this folder. Make sure that there are **//NO SPACES//** in the directory path. After extracting the archive the following folders should be present in the **//ADIEvalBoard//** folder: **//FPGA//**, **//Hdl//**, **//NiosCpu//**, **//Software//** and **//DataCapture//** .
^ **Folder** ^ **Description** ^
| FPGA | Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script //program_fpga.bat// the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. \\ The //ip// subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in ///hdl/src/HAL// and the AD7401 registers in ///hdl/src/inc//  |
| Hdl | Contains the source files for the AD7401 HDL driver: \\ - The //doc// subfolder contains a brief documentation for the core. \\ - The //src// subfolder contains the HDL source files.  \\ - The //tb// folder contains the sources of the core's testbench |
| NiosCpu | Contains the CED1Z Quartus evaluation project source files . The //ip// subfolder contains the AD7401 QSYS component |
| Software | Contains the source files of the Nios2 SBT evaluation project |
| DataCapture | Contains the script files used for data acquisition |

===== Install the USB-Blaster Device Driver =====

{{page>:resources:fpga:altera:ced1z:common_usb}}

======= AD7401 Evaluation Project Overview =======

The evaluation project contains all the source files needed to build a system that can be used to configure the AD7401 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.

===== CED1Z FPGA Design =====

The following components are implemented in the FPGA design:

^ Name                   ^ Address         ^ IRQ       ^
| CPU                    | 0x00000800      | -         |
| PLL                    | 0x00000000      | -         |
| ONCHIP_MEM             | 0x00002000      | -         |
| LEDS                   | 0x00000010      | -         |
| SYSID                  | 0x00000020      | -         |
| SRAM                   | 0x00200000      | -         |
| TRISTATE_BRIDGE_0      | -               | -         |
| JTAG_UART_0            | 0x00000030      | 1         |
| SYS_TIMER              | 0x00000040      | 2         |
| MM_CONSOLE_MASTER      | -               | -         |
| PWR_DATA               | 0x00000060      | -         |
| I2C_INT                | 0x00000080      | -         |
| PWR_EN_CLK             | 0x000000a0      | -         |
| AD7401_0              | 0x00000120      | -         |
|  **Table 1 System components**  |||

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the AD7401.

Table 2 describes the port definitions of the Avalon peripheral:

^ Port ^ Direction ^ Width ^ Description ^
| //**Generic pins**// ||||
| CLK_I                     | IN  | 1  | System clock. Designed with a 48 MHz clock |
| ADC_CLK_I                 | IN  | 1  | ADC Clock. Between 5 and 20 MHz. 19.2 MHz in this design. |
| RESET_I                   | IN  | 1  | System reset |
| //**Avalon Slave Interface**// ||||
| AVALON_WRITEDATA_I        | IN  | 32 | Slave write data bus |
| AVALON_WRITE_I            | IN  | 1  | Slave write data request |
| AVALON_READ_I             | IN  | 1  | Slave read data request |
| AVALON_ADDRESS_I          | IN  | 3  | Slave address bus |
| AVALON_READDATA_O         | OUT | 32 | Slave read data bus|
| //**Avalon Master Interface**// ||||
| AVALON_MASTER_WAITREQUEST | IN  | 1  | Master wait request signal |
| AVALON_MASTER_ADDRESS_O   | OUT | 32 | Master address bus |
| AVALON_MASTER_WRITE_O     | OUT | 1  | Master write signal |
| AVALON_MASTER_BYTEENABLE_O| OUT | 2  | Master byte enable signals |
| AVALON_MASTER_WRITEDATA_O | OUT | 16 | Master write data bus |
| //**External connectors**// ||||
| ADC_MDAT_I                | IN  | 1  | The single bit modulator output is supplied to this pin as serial data stream. The bits are clocked out on the rising edge of the ADC_MCLKOUT_I pin and are valid on the following MCLKOUT rising edge |
| ADC_MCLKIN_O              | OUT | 1  | Master clock logic input of the AD7401. The bit stream from the modulator is valid on the rising edge of MCLKOUT. |
|  **Table 2 Port description**  ||||

Table 3 describes the registers of the Avalon peripheral:

^ Name ^ Offset ^ Width ^ Access ^ Description ^
| CONTROL_REGISTER          | 0  | 32  | RW | Bit 0 is used to start data acquisition \\ Bit 1 is used to initiate software reset of the core \\ Bit 2 is used to configure the Avalon write master core to write data to the same location \\ Bit 3 is used to write data to the AD7401 evaluation board|
| ACQ_COUNT_REGISTER        | 1  | 32  | RW | Register used to configure the number of samples to be acquired when acquisition is started |
| BASE_REGISTER             | 2  | 32  | RW | Register used to configure the base address of the memory location where the acquired data is to be written |
| STATUS                    | 3  | 32  | R  | Bit 0 is used to signal that the acquisition is complete \\ Bit 1 is used to signal that the internal memory buffer has been overflown \\ Bit 2 is used to signal that the user has performed a write of a read only register register |
|  **Table 3 Register description**  |||||

The follwing figure presents the timing diagram for the read operations from the AD7401 driver.

{{ :resources:fpga:altera:ced1z:ad7401_read_timing.png?500 |Read operations time diagram}}

=== AD7401 module ===

This module is the actual driver of the AD7401 data acquisition system.

{{ :resources:fpga:altera:ced1z:ad7401_driver_pinout.png?400 | AD7401 driver pinout }}

^ Port ^ Direction ^ Width ^ Description ^
| //**General Connectors**// ||||
| FPGA_CLK_I                | IN  | 1  | 48 MHz clock |
| ADC_CLK_I                 | IN  | 1  | 5 to 20MHz clock signal. 19.2 MHz in this design |
| RESET_I                   | IN  | 1  | Module reset |
| //**CED1Z_interface connectors**// ||||
| DATA_O                    | OUT | 16 | Parallel bus to transfer the data to the upper module |
| DATA_RD_READY_O           | OUT | 1  | Signals that at port DATA_O there is new data available |
| //**AD7401 connectors**// ||||
| ADC_MDAT_I                | IN  | 1  | The single bit modulator output is supplied to this pin as serial data stream. The bits are clocked out on the rising edge of the ADC_MCLKOUT_I pin and are valid on the following MCLKOUT rising edge |
| ADC_MCLKIN_O              | OUT | 1  | Master clock logic input of the AD7401. The bit stream from the modulator is valid on the rising edge of MCLKOUT. |
|  **Table 4 Port description for the AD7401 module**  ||||

====== Quick Evaluation ======

The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.

Make sure the jumpers have the following configuration: J7-A ,J8-A, J9-C, J10-B, J11-B, J13-B, J14-C. Connect at J1 a +5V power supply.

In order to acquire data, follow the instructions in the //**Evaluation Project Data Acquisition**// section.

====== NIOS II Software Design ======

{{page>:resources:fpga:altera:ced1z:common_software_design}}

====== Evaluation Project Data Acquisition ======

After the FPGA is correctly programmed the data acquisition process can start by executing the data_capture.bat script. 

{{ :resources:fpga:altera:cedz:cmd_interface.png?500 |Demonstration Project Command Interface}}
  * A new acquisition can be started by executing the //**data_capture.bat**// script.

//**Note:**// If several consecutive data acquisitions are performed the captured data is appended to the **//Acquisition.csv//** file.

====== More information ======
  * [[ez>community/fpga|ask questions about the FPGA reference design]]
  * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
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