Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| resources:fpga:altera:bemicro:common_quick_eval [09 Nov 2011 14:33] – Approved Andrei Cozma | resources:fpga:altera:bemicro:common_quick_eval [15 Feb 2013 15:48] (current) – Updated the Demonstration Project User Interface name Adrian Costina | ||
|---|---|---|---|
| Line 1: | Line 1: | ||
| - | ======== Quick Evaluation ======== | ||
| - | |||
| The next sections of this lab present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system that can be used together with the uC-Probe interface for the ADI platform evalution. | The next sections of this lab present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load into the FPGA an image that contains a fully functional system that can be used together with the uC-Probe interface for the ADI platform evalution. | ||
| The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the **Quartus II Web Edition** tool or the [[https:// | The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the **Quartus II Web Edition** tool or the [[https:// | ||
| To load the FPGA image run the **// | To load the FPGA image run the **// | ||
| - | After the image was loaded the system must be reset. Now the FPGA contains a fully functional system and it is possible to skip directly to the **uC-Probe Interface** section of this lab. | + | After the image was loaded the system must be reset. Now the FPGA contains a fully functional system and it is possible to skip directly to the **DEMONSTRATION PROJECT USER INTERFACE** section of this lab. |
resources/fpga/altera/bemicro/common_quick_eval.1320845588.txt.gz · Last modified: 09 Nov 2011 14:33 by Andrei Cozma