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resources:fpga:altera:bemicro:adn2850 [26 Oct 2011 15:33] – [ADN2850: Nonvolatile Memory, Dual 1024-Position Digital Resistor] Andrei Cozma | resources:fpga:altera:bemicro:adn2850 [26 Jan 2021 01:22] (current) – update arrow links after their web site update Robin Getz | ||
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====== BeMicro FPGA Project for ADN2850 with Nios driver ====== | ====== BeMicro FPGA Project for ADN2850 with Nios driver ====== | ||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[adi> | ||
+ | |||
+ | ===== Evaluation Boards ===== | ||
+ | |||
+ | * [[adi> | ||
====== Overview ====== | ====== Overview ====== | ||
- | This lab presents the steps to setup an environment for using the **[[adi> | + | This lab presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
- | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
- | * a controller board, like the **[[resources/ | + | |
- | * an compatible Analog Devices SDP [[adi>sdp# | + | |
- | * corresponding PC software | + | |
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
Below is presented a picture of **SDP-B** Controller Board with the **EVAL-ADN2850SDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-ADN2850SDZ** Evaluation Board. | ||
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* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.arrownac.com/solutions/ | + | * [[https://www.intel.com/content/ |
* [[http:// | * [[http:// | ||
- | * [[http:// | + | * [[http:// |
====== Getting Started ====== | ====== Getting Started ====== | ||
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Below is presented the list of required hardware items: | Below is presented the list of required hardware items: | ||
- | * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board | + | * Arrow Electronics [[https://www.intel.com/content/www/ |
- | * [[http:// | + | * [[adi> |
* **EVAL-ADN2850SDZ** evaluation board | * **EVAL-ADN2850SDZ** evaluation board | ||
* Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | ||
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* [[http:// | * [[http:// | ||
* [[https:// | * [[https:// | ||
- | * [[http:// | + | * [[http:// |
- | * {{: | + | |
The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | The **Quartus II** design software and the **Nios II EDS** is available via the Altera Complete Design Suite DVD or by downloading from the web. | ||
- | The **Micrium uC/Probe Trial** version is available via download from the web at [[http:// | + | The **Micrium uC/Probe Trial** version |
+ | ===== Downloads ===== | ||
+ | * {{: | ||
===== Extract the Lab Files ===== | ===== Extract the Lab Files ===== | ||
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{{page> | {{page> | ||
+ | ====== Quick Evaluation ====== | ||
{{page> | {{page> | ||
+ | ====== FPGA Design ====== | ||
{{page> | {{page> | ||
+ | ====== NIOS II Software Design ====== | ||
{{page> | {{page> | ||
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{{page> | {{page> | ||
- |