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resources:fpga:altera:bemicro:ad7984 [13 Sep 2012 09:50] – Update reference project to Quartus 12.0 sp2. Acquisition is done using a simple TCL script. Adrian Costinaresources:fpga:altera:bemicro:ad7984 [26 Jan 2021 01:22] (current) – update arrow links after their web site update Robin Getz
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 ====== Overview ====== ====== Overview ======
  
-This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD7984SDZ]]** evaluation board together with the **[[http://www.arrownac.com/solutions/bemicro-sdk/|BeMicro SDK]]** USB stick, the Nios II Embedded Development Suite (EDS) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7984SDZ Evaluation Board with the BeMicro SDK Platform.+This lab presents the steps to setup an environment for using the **[[adi>EVAL-AD7984SDZ]]** evaluation board together with the **[[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]** USB stick, the Nios II Embedded Development Suite (EDS) and the [[https://www.micrium.com/ucprobe/about/|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD7984SDZ Evaluation Board with the BeMicro SDK Platform.
  
 {{ :resources:fpga:altera:bemicro:ad7984_bemicro.jpg?400 }} {{ :resources:fpga:altera:bemicro:ad7984_bemicro.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of: +{{page>common_sdp}}
-  *1.  A controller board like the SDP-B ( EVAL-SDP-CS1Z) +
-  *2.  The component SDP compatible product evaluation board +
-  *3.  Corresponding PC software ( shipped with the product evaluation board) +
-The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing. +
- +
-//**Note:**// it is expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7984SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7984SDZ** Evaluation Board.
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   * [[adi>AD7984|AD7984 Product Info]] - pricing, samples, datasheet   * [[adi>AD7984|AD7984 Product Info]] - pricing, samples, datasheet
   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7984SDZ evaluation board user guide}}   * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7984SDZ evaluation board user guide}}
-  * [[http://www.arrownac.com/solutions/bemicro-sdk|BeMicro SDK]]+  * [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]]
   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]   * [[http://www.altera.com/devices/processor/nios2|Nios II Embedded Development Suite (EDS)]]
  
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 Below is presented the list of required hardware items: Below is presented the list of required hardware items:
-  * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board +  * Arrow Electronics [[https://www.intel.com/content/www/us/en/programmable/b/bemicro-sdk.html|BeMicro SDK]] FPGA-based MCU Evaluation Board 
-  * [[http://www.arrownac.com/solutions/adi_interposer/|BeMicro SDK/SDP Interposer]] adapter board+  * [[adi>sdp-bemicro|BeMicro SDK/SDP Interposer]] adapter board
   * **EVAL-AD7984SDZ** evaluation board   * **EVAL-AD7984SDZ** evaluation board
   * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory   * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory
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 | ADC_CLK_I                 | IN  | 1  | Clock to be sent to the ADC during the conversion process. | | ADC_CLK_I                 | IN  | 1  | Clock to be sent to the ADC during the conversion process. |
 | //**IP control and data ports**// |||| | //**IP control and data ports**// ||||
-| DATA_O                    | OUT | 16 | Outputs the data read from the ADC. The channel ID is stored on the 4 most significant bits and the read data is stored on the 12 least significant bits. If the ADC is driven in word read mode then the channel ID will always be 0. |+| DATA_O                    | OUT | 18 | Outputs the data read from the ADC. |
 | DATA_RD_READY_O           | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | | DATA_RD_READY_O           | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. |
 | //**AD7984 control and data ports**// |||| | //**AD7984 control and data ports**// ||||
resources/fpga/altera/bemicro/ad7984.1347522641.txt.gz · Last modified: 13 Sep 2012 09:50 by Adrian Costina

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