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resources:fpga:altera:bemicro:ad7984 [13 Sep 2012 09:50] – Update reference project to Quartus 12.0 sp2. Acquisition is done using a simple TCL script. Adrian Costinaresources:fpga:altera:bemicro:ad7984 [12 Oct 2012 11:48] – [AD7984 Evaluation Project Overview] Andrei Cozma
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 {{ :resources:fpga:altera:bemicro:ad7984_bemicro.jpg?400 }} {{ :resources:fpga:altera:bemicro:ad7984_bemicro.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of: +{{page>common_sdp}}
-  *1.  A controller board like the SDP-B ( EVAL-SDP-CS1Z) +
-  *2.  The component SDP compatible product evaluation board +
-  *3.  Corresponding PC software ( shipped with the product evaluation board) +
-The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing. +
- +
-//**Note:**// it is expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7984SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7984SDZ** Evaluation Board.
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 | ADC_CLK_I                 | IN  | 1  | Clock to be sent to the ADC during the conversion process. | | ADC_CLK_I                 | IN  | 1  | Clock to be sent to the ADC during the conversion process. |
 | //**IP control and data ports**// |||| | //**IP control and data ports**// ||||
-| DATA_O                    | OUT | 16 | Outputs the data read from the ADC. The channel ID is stored on the 4 most significant bits and the read data is stored on the 12 least significant bits. If the ADC is driven in word read mode then the channel ID will always be 0. |+| DATA_O                    | OUT | 18 | Outputs the data read from the ADC. |
 | DATA_RD_READY_O           | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. | | DATA_RD_READY_O           | OUT | 1  | Active high signal to indicate the status of a read operation from the AD7984. The IP continuously reads the conversion results from the ADC and outputs them on the DATA_O bus. When this signal is high data can be read from the DATA_O bus. |
 | //**AD7984 control and data ports**// |||| | //**AD7984 control and data ports**// ||||
resources/fpga/altera/bemicro/ad7984.txt · Last modified: 26 Jan 2021 01:22 by Robin Getz

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