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resources:fpga:altera:bemicro:ad7657-1 [15 Oct 2012 17:04] – created Adrian Costina | resources:fpga:altera:bemicro:ad7657-1 [26 Jan 2021 01:22] (current) – update arrow links after their web site update Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This lab presents the steps to setup an environment for using the **[[adi> | + | This lab presents the steps to setup an environment for using the **[[adi> |
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* [[adi> | * [[adi> | ||
* EVAL-AD7657-1SDZ evaluation board user guide | * EVAL-AD7657-1SDZ evaluation board user guide | ||
- | * [[http://www.arrownac.com/solutions/ | + | * [[https://www.intel.com/content/ |
* [[http:// | * [[http:// | ||
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Below is presented the list of required hardware items: | Below is presented the list of required hardware items: | ||
- | * Arrow Electronics [[http://www.arrow.com/bemicrosdk/|BeMicro SDK]] FPGA-based MCU Evaluation Board | + | * Arrow Electronics [[https://www.intel.com/content/www/ |
- | * [[http:// | + | * [[adi> |
* **EVAL-AD7657_1SDZ** evaluation board | * **EVAL-AD7657_1SDZ** evaluation board | ||
* Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | * Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory | ||
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After the FPGA is correctly programmed the data acquisition process can start by executing the data_capture.bat script. The data_capture.tcl file can be modified to acquire a variable number of channels. | After the FPGA is correctly programmed the data acquisition process can start by executing the data_capture.bat script. The data_capture.tcl file can be modified to acquire a variable number of channels. | ||
- | <note>The configuration from data_capture.tcl is performed the first time the script is executed. If changes are performed after that, the system must be reinitialized by reprogramming the FPGA.</note> | + | <WRAP round help>The configuration from data_capture.tcl is performed the first time the script is executed. If changes are performed after that, the system must be reinitialized by reprogramming the FPGA.</WRAP> |
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