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--- resources:fpga:altera:bemicro:ad5684r [15 Feb 2013 15:05] – Updated uC/Probe related links Adrian Costina
+++ resources:fpga:altera:bemicro:ad5684r [11 Jan 2021 09:16] – Fixed bad link for AD5624R Ioana Chelaru
@@ Line 22: / Line 22: @@
 {{ :resources:fpga:altera:bemicro:ad5686r_sdp1z.png?400 }}
-The [[adi>AD564R]] is a low power, quad, 12-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance.
+The [[adi>AD5624R|AD564R]] is a low power, quad, 12-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance.
 The **EVAL-AD5684R** evaluation board is designed to help customers quickly prototype new AD5684R circuits and reduce design time. The board requires ±5 V supplies. These are used to power the output amplifier and Vref.

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