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resources:eval:user-guides:xud1a:user-guide [19 Sep 2022 12:46] – [PMOD Pinout] fixed part link Sam Ringwoodresources:eval:user-guides:xud1a:user-guide [19 May 2023 20:01] (current) – [Software/Digital Control] Sam Ringwood
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 {{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_top-web.gif?400 |}} {{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_top-web.gif?400 |}}
-<WRAP centeralign>**//Figure 1: ADXUD1AEBZ Board//**</WRAP>+<WRAP centeralign>**//Figure 1: ADXUD1AEBZ Board: Front//**</WRAP> 
 + 
 +{{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_bottom.jpg?400 |}} 
 +<WRAP centeralign>**//Figure 2: ADXUD1AEBZ Board: Back//**</WRAP>
  
 ---- ----
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 === SDP Control === === SDP Control ===
   * [[http://swdownloads.analog.com/ACE/SDP/SDPDrivers.exe|SDP Drivers]]   * [[http://swdownloads.analog.com/ACE/SDP/SDPDrivers.exe|SDP Drivers]]
-  * {{ :resources:eval:user-guides:xud1a:sdp_xud1a.zip |Basic SDP Test Program}} (Windows 10 might try to block this, you'll have to explicitly allow it in your security settings)+  * {{ :resources:eval:user-guides:xud1a:sdp_xud1a.zip |Basic SDP-S Test Program Rev A}}  
 +  * {{ {{ :resources:eval:user-guides:xud1a:sdps_xud1a_r1.zip | Basic SDP-S Test Program Rev B}}  
 +<note>Windows 10 might try to block the example Test Program, you'll have to explicitly allow it in your security settings</note>
   * [[adi>sdp-s|SDP-S controller board]]   * [[adi>sdp-s|SDP-S controller board]]
  
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 {{ :resources:eval:user-guides:xud1a:xud1a_revd_blockdiagram.png |}} {{ :resources:eval:user-guides:xud1a:xud1a_revd_blockdiagram.png |}}
-<WRAP centeralign>**//Figure 2: ADXUD1AEBZ Block Diagram//**</WRAP>+<WRAP centeralign>**//Figure 3: ADXUD1AEBZ Block Diagram//**</WRAP>
  
 ===== LO Signal Chain ===== ===== LO Signal Chain =====
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 By default, the board populates C165 for an external LO source with C61 not installed. The user can remove C165 and re-install on the C61 pad to enabled use of the ADF4371. When using the onboard ADF4371, the default reference is the onboard VCXO with C372 installed and C373 not installed. The user can remove C372 and re-install on the C373 pad to enabled use of the external reference port J3. By default, the board populates C165 for an external LO source with C61 not installed. The user can remove C165 and re-install on the C61 pad to enabled use of the ADF4371. When using the onboard ADF4371, the default reference is the onboard VCXO with C372 installed and C373 not installed. The user can remove C372 and re-install on the C373 pad to enabled use of the external reference port J3.
  
 +<note>An external LO source is recommended for performance based measurements. The on-board ADF4371 is provided for convenience to allow stand-alone operation of the hardware for a wide range of operational frequencies. A bandpass filter should be inserted in the ADF4371 PLL output path depending on the final frequency plan to reject the harmonic content generated by the ADF4371 internal multipliers.</note>
 ===== Digital Control ===== ===== Digital Control =====
 ==== PMOD Pinout ==== ==== PMOD Pinout ====
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 {{ :resources:eval:user-guides:xud1a:xud1a_pmod.png?400 |}} {{ :resources:eval:user-guides:xud1a:xud1a_pmod.png?400 |}}
-<WRAP centeralign>**//Figure 3: ADXUD1AEBZ PMOD Pinout//**</WRAP>+<WRAP centeralign>**//Figure 4: ADXUD1AEBZ PMOD Pinout//**</WRAP>
  
 ==== Interposer Board ==== ==== Interposer Board ====
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 {{ :resources:eval:user-guides:xud1a:xud1a_sdps.png? |}} {{ :resources:eval:user-guides:xud1a:xud1a_sdps.png? |}}
-<WRAP centeralign>**//Figure 4: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP>+<WRAP centeralign>**//Figure 5: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP> 
 + 
 +==== Control Logic ==== 
 +The PMOD inputs are fed to a buffer and logic network for simplified board control and quick switching time.  
 + 
 +{{ :resources:eval:user-guides:xud1a:xud1a_controlblockdiagram.png?600 |}} 
 +<WRAP centeralign>**//Figure 6: ADXUD1AEBZ Control Block Diagram//**</WRAP> 
 + 
 + 
 +^ Channel ^  Mode  ^ TXRX0 ^ TXRX1 ^ TXRX2 ^ TXRX3 ^ Rx Gain Mode ^ 
 +|     A    |    TX    |    1    |    -    |    -    |    -    |    0    | 
 +|     :::    |    RX Low Gain    |    0    |    -    |    -    |    -    |    0    | 
 +|     :::    |    RX High Gain    |    0    |    -    |    -    |    -    |    1    | 
 +|     B    |    TX    |    -    |    1    |    -    |    -    |    0    | 
 +|     :::    |    RX Low Gain    |    -    |    0    |    -    |    -    |    0    | 
 +|     :::    |    RX High Gain    |    -    |    0    |    -    |    -    |    1    | 
 +|     C    |    TX    |    -    |    -    |    1    |    -    |    0    | 
 +|     :::    |    RX Low Gain    |    -    |    -    |    0    |    -    |    0    | 
 +|     :::    |    RX High Gain    |    -    |    -    |    0    |    -    |    1    | 
 +|     D    |    TX    |    -    |    -    |    -    |    1    |    0    | 
 +|     :::    |    RX Low Gain    |    -    |    -    |    -    |    0    |    0    | 
 +|     :::    |    RX High Gain    |    -    |    -    |    -    |    0    |    1    | 
 +<WRAP centeralign>**//Table 1: ADXUD1AEBZ RF Control Logic//**</WRAP>
  
 +^  ADF4371 Output  ^  PLL_OUTPUT_SEL  ^
 +|     8 - 16 GHz    |    1   |
 +|     16 - 32 GHz    |    0   |
 +<WRAP centeralign>**//Table 2: ADXUD1AEBZ ADF4371 Control Logic//**</WRAP>
  
 ====== Evaluation ====== ====== Evaluation ======
resources/eval/user-guides/xud1a/user-guide.1663584385.txt.gz · Last modified: 19 Sep 2022 12:46 by Sam Ringwood

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