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resources:eval:user-guides:xud1a:user-guide [19 Sep 2022 12:46] – [PMOD Pinout] fixed part link Sam Ringwood | resources:eval:user-guides:xud1a:user-guide [26 Jan 2023 17:22] – added control logic section & info Sam Ringwood |
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{{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_top-web.gif?400 |}} | {{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_top-web.gif?400 |}} |
<WRAP centeralign>**//Figure 1: ADXUD1AEBZ Board//**</WRAP> | <WRAP centeralign>**//Figure 1: ADXUD1AEBZ Board: Front//**</WRAP> |
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| {{ :resources:eval:user-guides:xud1a:eval-adxud1aebz_bottom.jpg?400 |}} |
| <WRAP centeralign>**//Figure 2: ADXUD1AEBZ Board: Back//**</WRAP> |
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{{ :resources:eval:user-guides:xud1a:xud1a_revd_blockdiagram.png |}} | {{ :resources:eval:user-guides:xud1a:xud1a_revd_blockdiagram.png |}} |
<WRAP centeralign>**//Figure 2: ADXUD1AEBZ Block Diagram//**</WRAP> | <WRAP centeralign>**//Figure 3: ADXUD1AEBZ Block Diagram//**</WRAP> |
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===== LO Signal Chain ===== | ===== LO Signal Chain ===== |
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{{ :resources:eval:user-guides:xud1a:xud1a_pmod.png?400 |}} | {{ :resources:eval:user-guides:xud1a:xud1a_pmod.png?400 |}} |
<WRAP centeralign>**//Figure 3: ADXUD1AEBZ PMOD Pinout//**</WRAP> | <WRAP centeralign>**//Figure 4: ADXUD1AEBZ PMOD Pinout//**</WRAP> |
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==== Interposer Board ==== | ==== Interposer Board ==== |
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{{ :resources:eval:user-guides:xud1a:xud1a_sdps.png? |}} | {{ :resources:eval:user-guides:xud1a:xud1a_sdps.png? |}} |
<WRAP centeralign>**//Figure 4: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP> | <WRAP centeralign>**//Figure 5: ADXUD1AEBZ Interposer Pinout with SDP-S Connector//**</WRAP> |
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| ==== Control Logic ==== |
| The PMOD inputs are fed to a buffer and logic network for simplified board control and quick switching time. |
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| {{ :resources:eval:user-guides:xud1a:xud1a_controlblockdiagram.png?600 |}} |
| <WRAP centeralign>**//Figure 6: ADXUD1AEBZ Control Block Diagram//**</WRAP> |
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| ^ Channel ^ Mode ^ TXRX0 ^ TXRX1 ^ TXRX2 ^ TXRX3 ^ Rx Gain Mode ^ |
| | A | TX | 0 | - | - | - | 0 | |
| | ::: | RX Low Gain | 1 | - | - | - | 0 | |
| | ::: | RX High Gain | 1 | - | - | - | 1 | |
| | B | TX | - | 0 | - | - | 0 | |
| | ::: | RX Low Gain | - | 1 | - | - | 0 | |
| | ::: | RX High Gain | - | 1 | - | - | 1 | |
| | C | TX | - | - | 0 | - | 0 | |
| | ::: | RX Low Gain | - | - | 1 | - | 0 | |
| | ::: | RX High Gain | - | - | 1 | - | 1 | |
| | D | TX | - | - | - | 0 | 0 | |
| | ::: | RX Low Gain | - | - | - | 1 | 0 | |
| | ::: | RX High Gain | - | - | - | 1 | 1 | |
| <WRAP centeralign>**//Table 1: ADXUD1AEBZ RF Control Logic//**</WRAP> |
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| ^ ADF4371 Output ^ PLL_OUTPUT_SEL ^ |
| | 8 - 16 GHz | 1 | |
| | 16 - 32 GHz | 0 | |
| <WRAP centeralign>**//Table 2: ADXUD1AEBZ ADF4371 Control Logic//**</WRAP> |
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====== Evaluation ====== | ====== Evaluation ====== |