The following “shopping list” details what is provided when purchasing the hardware herein and what a user needs to procure separately.
Connect the Stingray board to the PMOD connectors on the ZCU102 as described below:
Figure 3: ZCU102-Stingray Digital Connections
Connect the XUD1A evaluation board to the ZCU102's HPC1 port. The FMC extension is used both to move the interposer board and XUD1A away from the MxFE evaluation board as well as to allow access to the HPC1 connector which is otherwise blocked by the MxFE evaluation board.
Figure 4: ZCU102-XUD1A Digital Connections
Connect the MxFE evaluation board to the ZCU102's HPC0 port as shown below.
Figure 5: ZCU102-AD9081 Attachment
The platform is divided into four 8:1 subarrays as detailed in the below figure. Two ADAR1000s are connected via RF Splitter/Combiner to a single up/down converter channel on the ADXUD1AEBZ. The IF portion of an individual up/down converter channel is split to a TX IF and RX IF input/out. Each IF output is directly connected to its respective ADC and DAC.
Figure 6: Inter-Board Connections Diagram
Connect the MxFE and XUD1A together using SMA-SMPM cables as indicated below:
|Connection #||MxFE Connector||RF Filter||XUD1A Connector|
|1||ADC3 (SMA)||VLF-8400+||J10 (SMPM)|
|2||ADC1 (SMA)||VLF-8400+||J8 (SMPM)|
|3||DAC3 (SMA)||VLF-5500+||J9 (SMPM)|
|4||DAC2 (SMA)||VLF-5500+||J7 (SMPM)|
|5||DAC1 (SMA)||VLF-5500+||J5 (SMPM)|
|6||DAC0 (SMA)||VLF-5500+||J1 (SMPM)|
|7||ADC0 (SMA)||VLF-8400+||J6 (SMPM)|
|8||ADC2 (SMA)||VLF-8400+||J2 (SMPM)|
The XUD1A has 4 RFIO ports whereas the Stingray board has 8 RFIO ports. For this system, the Stingray's 8 channels will be paired using external splitter/combiners (Recommended Splitter/Combiner) to create 4 digital channels which can interface with the XUD1A and MxFE thus created four subarrays where each subarray consists of eight analog channels each. The below tables show how these connections are to be made.
|Connection #||Stingray Connectors||Splitter # (Ports 1/2)|
|1||J1, J3 (SMPM)||1 (SMA)|
|2||J2, J4 (SMPM)||2 (SMA)|
|3||J6, J8 (SMPM)||3 (SMA)|
|4||J5, J7 (SMPM)||4 (SMA)|
|Connection #||XUD1A Connector||Splitter # (Sum Port)|
|1||J1D (SMA)||1 (SMA)|
|2||J1C (SMA)||2 (SMA)|
|3||J1B (SMA)||3 (SMA)|
|4||J1A (SMA)||4 (SMA)|
The default clocking scheme used for the AD9081-FMCA-EBZ uses the on-chip PLL. The HMC7044 provides the reference into the chip derived from the on-board VCXO crystal oscillator. An external reference signal can be applied to the HMC7044 if a the reference signal requires phase lock to other test equipment used in evaluation. The AD9081 firmware contains a HMC7044 reference clock priority table. No firmware changes are required if the reference clock is supplied via EXT_HMCREF SMP-F connection.
Figure 7: AD9081 Clocking Block Diagram
The MxFE Evaluation Platform has provisions for directly driving the sampling clock of the MxFE data converter. An SMP-F plug is available for this purpose, which connects to an AC-coupling capacitor that is not populated by default. Reference the schematic for more information. The table below lists the modifications required for direct clocking.
Figure 8: AD9081 Direct Clocking Implementation
|Direct Clocking Modifications|
|SMP-F Ref Des||Modifications|
|EXT_CLK||Depopulate C3D/C5D, Populate C4D/C6D|
The default LO configuration for the XUD1A is for an external LO via SMA-F connector. The LO is common across all 4 up/down converter channels via splitter network. Refer to the XUD1A Block Diagram for more details.
Figure 9: XUD1A LO Block Diagram
The on-board ADF4371 PLL can be used in lieu of an external LO signal. The default ADF4371 reference clock is an on-board 100 MHz VCXO crystal oscillator, but provisions are available to provide an external reference via a SMP-F connector.
Figure 10: XUD1A On-Board PLL Implementation
The table below lists the modifications required for the on-board LO.
|XUD1A On-Board LO Modifications|
|ADF4371 Output||Depopulate C165, Populate C61|
|ADF4371 External Reference||Depopulate C372, Populate C373|
|ADF4371 +5V Enable||Populate R20 with 0 Ohm 0402 Resistor|
The system platform is capable of Time Division Duplexing (TDD) is controlled using a TDD Engine implemented in firmware. The TDD engine controls the MxFE TX and RX data enable paths, the ADXUD1AEBZ up/down converter circuitry and ADAR1000EVAL1Z RF circuitry. See the Matlab Control Overview section for user-level control.
Replicated IO for the TDD controller is created in hardware all tied to a common software control. The replicas of the MxFE datapath enable pins are routed to signal nets on the ADXUD1AEBZ Interposer board.
|Signal||ZCU102 FPGA Pin (U1)||ZCU102 FMC HPC1 Connector (J4)||Interposer Board (P3)|
|MxFE TX EN||AG3||D11||IMU_GPIO0|
|MxFE RX EN||AH3||D12||IMU_GPIO1|
The control logic for the RF switching is common between the ADAR1000EVAL1Z and the ADXUD1AEBZ. The TR_EN probe point on the secondary side of the ADAR1000EVAL1Z is recommended to use for connecting a measurement probe.
Figure 11: ADAR1000EVAL1Z TR Probe
There are two potential issues that prevent the 1.8V VADJ from powering on the AD9081-FMCA-EBZ board. Upon boot, the FPGA queries the EEPROM of the different boards attached. If a non-compliant EEPROM is detected, the VADJ stays low during boot thus preventing the AD9081 board from powering on.
Currently, the FMC EEPROM of the interposer board used for the ADXUD1AEBZ is not factory programmed. The user must execute some commands within a UART terminal to program the FMC EEPROM. The command sets to program the FMC EEPROM of the ADXUD1AEBZ interposer board are detailed on the software wiki. Reboot the FPGA after programming the FMC EEPROM.
The AD9081 LTM4616 power module run control pin voltage threshold is 1.7V. Verify the voltage and resistance of the R1M resistor on the AD9081-FMCA-EBZ exceed the voltage threshold of 1.7V. If not, measure the R1M resistor and verify the resistance value is 2.2 kΩ. The resistor can be replaced with a 0402 220 Ω resistor to meet the voltage threshold requirements of the power module.
Figure 12: AD9081-FMCA-EBZ R1M Location