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--- resources:eval:user-guides:spi [13 May 2022 17:41] – m valerie hamilton
+++ resources:eval:user-guides:spi [18 May 2022 13:59] (current) – final edit valerie hamilton
@@ Line 8: / Line 8: @@
 === SPI Modes ===
-SPI has 4 modes that it operates in. The CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. CPOL and CPHA bits decide on which edge is the data sampled and shifted. The Mode Table below demonstrates SPI modes. The AD5758 (and all other generics listed in the INFO) can be used in either mode 1 or mode 2.
+SPI has 4 modes that it operates in. The CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. The CPOL and CPHA bits decide on which edge the data is sampled and shifted. The Mode Table below demonstrates SPI modes. The AD5758 (and all other generics listed in the INFO) can be used in either mode 1 or mode 2.
 ===SPI Mode Table===
@@ Line 16: / Line 16: @@
 |  2  |      1   |           0        |  Logic High  | Data shifted out on the rising edge and sampled on the falling edge|
 |  3  |      1   |           1        |  Logic High  | Data shifted out on the falling edge and sampled on the rising edge|
 === SPI Cyclic Redundancy Check (CRC)===
 To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. The device controlling the AD5758 generates an 8-bit frame check sequence using the following polynomial:\\
   *<m>C(x) = x^8 + x^2 + x^1 + 1</m>\\
-This sequence is added to the end of the data-word, and 32 bits are sent to the AD5758 before taking SYNC high.
+This sequence is added to the end of the 24 bit data-word, and 32 bits are sent to the AD5758 before taking SYNC high.
 If the CRC check is valid, the data is written to
 the selected register. If the CRC check fails, the data is ignored and
-the SPI_CRC_ERR bit is set. The SPI CRC feature can be used for both the
+the SPI_CRC_ERR bit is set along with the fault pin being asserted. The SPI CRC feature can be used for both the
 transmission and receipt of data packets. The CRC is enabled by default so the user must
 supply a frame of exactly 32 bits wide that contains the 24 data bits
-and 8-bit CRC for the first SPI write. To disable the CRC (Bit SPI_CRC_EN) it is recommended to do this after the calibration memory refresh step.
+and 8-bit CRC for the first SPI write. To disable the CRC (Bit 0 SPI_CRC_EN in register 0x10) it is recommended to do this after the calibration memory refresh step.
 ===Writing to a Register===
@@ Line 38: / Line 40: @@
 |  Slip Bit    |  Address Bits    |  Register Address        |  Data  |  CRC  |
-With SPI CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first as a 32-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. \\
+With CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first, under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. \\
 ===Reading a Register===
@@ Line 52: / Line 54: @@
 Figures 1 and 2 show the first and second software reset key writes. The first write of 0x8815FAA4 can be decoded as
-^  Bits 31:24  ^  Bits 23:16  ^  Bits 15:8  ^  Bits 7:0  ^
-|  0x88  |  0x15  |  0xFA  |  0xA4  |
+^  D31      ^  D30:D29       ^   D28:D24             ^  D23:D8   ^  D7:D0  ^
-|  10001000  |  00010101  |  11111010  |  10100100  |
+|  Slip Bit    |  Address Bits    |  Register Address        |  Data  |  CRC  |
-Slip Bit = 1,  Address Bits = 00,   Register Address = 0x08, Data = 0x15FA, CRC = 0xA4 \\ For the second write the data has changed to 0xFA51 and the CRC changed to 0x31.
+|  1  |  00  |   0x08 (01000)  |  0x15FA  |   0xA4  |
+For the second write the data has changed to 0xFA51 and the CRC changed to 0x31.
@@ Line 61: / Line 65: @@
 <fc #ff00ff>**SCLK**</fc> --> SPI clock\\
 <fc #008000>**SYNC**</fc> --> SYNC signal (must be taken low to initiate SPI transfer)\\
-<fc #f0e68c>**SDI**</fc> --> Serial Data In\\
+<fc #f0e68c>**SDI**</fc> --> Serial Data In (Top line of S1 serial bus)\\
-<fc #6495ed>**SDO**</fc> --> Serial Data Out\\
+<fc #6495ed>**SDO**</fc> --> Serial Data Out (Bottom line of S1 serial bus)\\
-\\
+**In the following examples the software driver is configured for SPI mode 1 and the CRC is enabled.**\\ \\
 {{ :resources:eval:user-guides:1st_rst_key.png?nolink&700 |}}
@@ Line 76: / Line 79: @@
 </WRAP>
-Figure 3 shows a readback of the default state of the digital diagnostic results register (Address 0x14). There are 2 SPI frames visible in the scope plot. Figures 4 and 5 show the first and second SPI frames respectively. The first being the readback command and the second shows the NOP command along with the readback data on SDO. The readback data 0x942000 on SDO can be decoded as Slip Bit = 1,  Address Bits = 00,   Register Address = 0x08, Data = 0x15FA, CRC = 0xA4
+Figure 3 shows a readback of the default state of the digital diagnostic results register (Address 0x14) before the calibration memory has been refreshed. There are 2 SPI frames visible in the scope plot. Figures 4 and 5 show the first and second SPI frames respectively. The first being the readback command to read the digital diagnostic results register (Address 0x14) and the second shows the NOP command along with the readback data on SDO. The readback data 0x94A0001A on SDO can be decoded as Bits 31:30 = 10,  Fault pin status = 0. Register Address = 0x14, Data = 0xA000 (CAL_MEM_UNREFRESHED = 1 and RESET_OCCURED = 1), CRC = 0x1A
 {{ :resources:eval:user-guides:spi_2_stg_rd.png?nolink&700 |}}
@@ Line 84: / Line 87: @@
-{{ :resources:eval:user-guides:cslm.png?nolink&700 |}}
+{{ :resources:eval:user-guides:dig_read.png?nolink&700 |}}
 <WRAP centeralign>
-//Figure 4 Two Stage Readback command - first frame//
+//Figure 4 Two Stage Readback command - first frame write 0x93001478//
 </WRAP>
 {{ :resources:eval:user-guides:rst_sdo_read.png?nolink&700 |}}
 <WRAP centeralign>
-//Figure 5 Two Stage Readback command - second frame including SDO data//
+//Figure 5 Two Stage Readback command - second frame write 0x8000000B (including SDO data 0x94A0001A)//
 </WRAP>
 === Calibration Memory Refresh ===
-After performing a software or hardware reset the next write **must** be a calibration memory refresh. The refresh is performed by writing the key 0xFCBA to the key register (address 0x08). Figure 6 shows the calibration memory refresh SPI write.
+After performing a software or hardware reset the next write **must** be a calibration memory refresh. The refresh is performed by writing the key 0xFCBA to the key register (address 0x08). The calibration memory refresh SPI write is 0x88FCBA9D.
-{{ :resources:eval:user-guides:cal_mem1.png?nolink&700 |}}
-<WRAP centeralign>
-//Figure 6 Calibration Memory Refresh Write//
-</WRAP>
 ===Disabling CRC===
-After performing a calibration refresh the CRC can be disabled if desired. The command to disable the CRC is  Figure 4 shows the SPI write to clear the reset occurred bit. The SPI write to disable the CRC is 0x50005CB7 (Assuming address bits AD0 and AD1 are logic 0 on the hardware).
+After performing a calibration refresh the CRC can be disabled if desired. The command to disable the CRC is  Figure 4 shows the SPI write to clear the reset occurred bit. The SPI write to disable the CRC is 0x50005CB7.
-{{ :resources:eval:user-guides:dis_crc1.png?nolink&700 |}}
-<WRAP centeralign>
-//Figure 8: SPI frame to disable the CRC//
-</WRAP>
 ===Clearing Reset Occurred===
-After performing a calibration refresh the device can now be configured as required. The reset occurred bit (Bit 13) in the digital diagnostic results register (Address 0x14) is a logic high and should be cleared. To clear the bit a "1" must be written to clear the bit to a logic 0. Figure 4 shows the SPI write to clear the reset occurred bit.
+After performing a calibration refresh the device can now be configured as required. The reset occurred bit (Bit 13) in the digital diagnostic results register (Address 0x14) is a logic high and should be cleared. To clear the bit a "1" must be written to clear the bit to a logic 0. The SPI write to clear the reset occurred bit is 0x942000AC.
-{{ :resources:eval:user-guides:rst_occ.png?nolink&700 |}}
-<WRAP centeralign>
-//Figure 7: RESET_OCCURED Bit Being Cleared//
-</WRAP>
-{{ :resources:eval:user-guides:rst_occ.png?nolink&700 |}}
-<WRAP centeralign>
-//Figure 6: RESET_OCCURED Bit Being Cleared//
-</WRAP>
-{{ :resources:eval:user-guides:rst_occ.png?nolink&700 |}}
-<WRAP centeralign>
-//Figure 7: RESET_OCCURED Bit Being Cleared//
-</WRAP>

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