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Serial Peripheral Interface on AD5758

The AD5758/ADFS5758/AD5753/AD5423/AD5413 contain the same serial peripheral interface and follow the below guide.

The AD5758 is controlled over a 4-wire serial interface with an 8-bit cyclic redundancy check (CRC-8) enabled by default. The input shift register is 32 bits wide, and data is loaded into the device MSB first under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. The purpose of this guide is to explain how the AD5758 SPI works and show examples of the first required SPI writes including CRC as recommended in Figure 90 of the AD5758 datasheet.

SPI Modes

SPI has 4 modes that it operates in. The CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. CPOL and CPHA bits decide on which edge is the data sampled and shifted. The Mode Table below demonstrates SPI modes. The AD5758 (and all other generics listed in the INFO) use SPI mode 1.

SPI Mode Table

SPI Mode	CPOL	CPOH	Clock Polarity in Idle State	Clock phase used to Sample Edge
0	0	0	Logic Low	Data sampled on rising edge and shifted out on the falling edge
1	0	1	Logic Low	Data sampled on the falling edge and shifted out on the rising edge
2	1	0	Logic High	Data sampled on the rising edge and shifted out on the falling edge
3	1	1	Logic High	Data sampled on the falling edge and shifted out on the rising edge

SPI Cyclic Redundancy Check (CRC)

To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. The device controlling the AD5758 generates an 8-bit frame check sequence using the following polynomial:

This sequence is added to the end of the data-word, and 32 bits are sent to the AD5758 before taking SYNC high.

If the CRC check is valid, the data is written to the selected register. If the CRC check fails, the data is ignored and the SPI_CRC_ERR bit is set. The SPI CRC feature can be used for both the transmission and receipt of data packets. The CRC is enabled by default so the user must supply a frame of exactly 32 bits wide that contains the 24 data bits and 8-bit CRC for the first SPI write. To disable the CRC (Bit SPI_CRC_EN) it is recommended to do this after the calibration memory refresh step.

Writing to a Register

As shown in the SPI Write Frame table, every SPI write frame contains a slip bit, two address bits, a register address, data and if enabled the CRC will be appended to the SPI frame creating a 32 bit frame. The slip bit must equal the inverse of the MSB − 1 for the frame to be considered valid. The address bits must match the hardware address pins (AD0 and AD1) for a particular device to accept the SPI frame on the bus. The register address is the address the data should be written to.

SPI Write Frame

D31	D30:D29	D28:D24	D23:D8	D7:D0
Slip Bit	Address Bits	Register Address	Data	CRC

With SPI CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first as a 32-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored.

Performing a Software Reset

Before initially configuring the device, it is good practice to perform either a hardware or software reset. A software reset is performed by writing 2 keys in sequence to the key (address 0x08) register.

Figure 1 shows the first of the key writes to reset the AD5758. The data 0x8815FAA4 can be decoded as

Bits 31:24	Bits 23:16	Bits 15:8	Bits 7:0
0x88	0x15	0xFA	0xA4
10001000	00010101	11111010	10100100

Slip Bit = 1
Address Bits = 00
Register Address= 0x08
Data = 0x15FA
CRC = 0xA4

The oscilloscope plots below show each of the 4 SPI wire data:
SCLK --> SPI clock
SYNC --> SYNC signal (must be taken low to initiate SPI transfer)
SDI --> Serial Data In
SDO --> Serial Data Out

Figure 1 Software Reset Key1 Write

Figure 2 Software Reset Key2 Write

Calibration Memory Refresh

After performing a software or hardware reset the next write must be a calibration memory refresh. The refresh is performed by writing the key 0xFCBA to the key register (address 0x08). Figure 3 shows the calibration memory refresh SPI write.

Figure 3 Calibration Memory Refresh Write

Clearing Reset Occurred

After performing a calibration refresh the device can now be configured as required. The reset occurred bit (Bit 13) in the digital diagnostic results register (Address 0x14) is a logic high and should be cleared. To clear the bit a “1” must be written to clear the bit to a logic 0. Figure 4 shows the SPI write to clear the reset occurred bit.

Figure 4: RESET_OCCURED Bit Being Cleared

Reading a Register

The default mode for reading back a register is called the two stage readback mode. This mode consists of a write to the TWO_ STAGE_READBACK_SELECT register (Address 0x13) to select the register location to be read back, followed by a NOP command. To perform a NOP command, write all zeros to Bits[D15:D0] of the NOP register (Address 0x00). Figure 5 shows a readback of the default state DAC Config Register (Address 0x06). There are 2 SPI frames visible in the scope plot. Figures 6 and 7 show the first and second SPI frames respectively.

Figure 5: RESET_OCCURED Bit Being Cleared

Figure 6: RESET_OCCURED Bit Being Cleared

Figure 7: RESET_OCCURED Bit Being Cleared

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