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resources:eval:user-guides:spi [10 May 2022 10:34] – edit Erlandas Petkeviciusresources:eval:user-guides:spi [18 May 2022 13:59] (current) – final edit valerie hamilton
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-===== Serial Peripheral Interface on AD5758 =====+==== Using the Serial Peripheral Interface on the AD5758 ====
  
 +<WRAP info>
 +The **AD5758/ADFS5758/AD5753/AD5423/AD5413** contain the same serial peripheral interface and follow the below guide.
 +</WRAP>
  
-==== Slip Bit ==== +The AD5758 is controlled over a 4-wire serial interface with an 8-bit cyclic redundancy check (CRC-8) enabled by default. The input shift register is 32 bits wide, and data is loaded into the device MSB first under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. The purpose of this guide is to explain how the AD5758 SPI works and show examples of the first required SPI writes including CRC as recommended in Figure 90 of the AD5758 datasheet. \\ 
-A further enhancement to the robustness of the interface is the  +
-addition of the slip bit. The MSB of the SPI frame must equal  +
-the inverse of the MSB − 1 for the frame to be considered valid. If an incorrect slip bit is detected, the data is ignored and the  +
-SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register +
-is asserted.+
  
 +=== SPI Modes ===
 +SPI has 4 modes that it operates in. The CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. The CPOL and CPHA bits decide on which edge the data is sampled and shifted. The Mode Table below demonstrates SPI modes. The AD5758 (and all other generics listed in the INFO) can be used in either mode 1 or mode 2. 
  
-==== AD5758 Address Bits ====  +===SPI Mode Table===  
-The AD5758 address pins (AD0 and AD1) are used in  +^ SPI Mode ^ CPOL       ^ CPHA             ^Clock Polarity in Idle State ^ Clock phase used to Sample Edge^ 
-conjunction with the address bits within the SPI frame to determine which AD5758 device is being  +|  0  |  0   |           0        |  Logic Low  | Data shifted out on falling edge and sampled on the rising edge| 
-addressed by the system controller. With the two address pins,  +|  1  |      0   |           1        |  Logic Low  | Data shifted out on the rising edge and sampled on the falling edge| 
-up to four devices can be independently addressed on one board.+|  2  |      1   |           0        |  Logic High  | Data shifted out on the rising edge and sampled on the falling edge| 
 +|  3  |      1   |           1        |  Logic High  | Data shifted out on the falling edge and sampled on the rising edge|
  
-==== SPI Cyclic Redundancy Check ==== 
-To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. 
-The device controlling the AD5758 generates an 8-bit frame  
-check sequence using the following polynomial: 
-C(x) = x8 + x2 + x1 + 1 
-This sequence is added to the end of the data-word, and 32 bits  
-are sent to the AD5758 before taking SYNC high. 
  
-If the SPI_CRC_EN bit is set high (default state), the user must +=== SPI Cyclic Redundancy Check (CRC)=== 
 +To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. The device controlling the AD5758 generates an 8-bit frame check sequence using the following polynomial:\\  
 +  *<m>C(x) = x^8 + x^2 + x^1 + 1</m>\\  
 +This sequence is added to the end of the 24 bit data-word, and 32 bits are sent to the AD5758 before taking SYNC high. 
 + 
 +If the CRC check is valid, the data is written to  
 +the selected register. If the CRC check fails, the data is ignored and  
 +the SPI_CRC_ERR bit is set along with the fault pin being asserted. The SPI CRC feature can be used for both the  
 +transmission and receipt of data packets. The CRC is enabled by default so the user must 
 supply a frame of exactly 32 bits wide that contains the 24 data bits  supply a frame of exactly 32 bits wide that contains the 24 data bits 
-and 8-bit CRC. If the CRC check is valid, the data is written to  +and 8-bit CRC for the first SPI write. To disable the CRC (Bit 0 SPI_CRC_EN in register 0x10) it is recommended to do this after the calibration memory refresh step. 
-the selected register. If the CRC check fails, the data is ignored,  +
-the FAULT pin goes low and the FAULT pin status bit and the  +
-digital diagnostic status bit (DIG_DIAG_STATUS) in the status  +
-register are asserted. A subsequent readback of the +
-DIGITAL_DIAG_RESULTS register reveals that the  +
-SPI_CRC_ERR bit is also set. This register is a per bit, write to  +
-clear register (see the Sticky Diagnostic Results Bits section); +
-therefore, the SPI_CRC_ERR bit can be cleared by writing a 1 to  +
-Bit D0 of the DIGITAL_DIAG_RESULTS register. Doing so  +
-clears the SPI_CRC_ERROR bit and causes the FAULT pin to  +
-return high (assuming that there are no other active faults). +
-When configuring the FAULT_PIN_CONFIG register, the user  +
-can decide whether the SPI CRC error affects the FAULT pin.  +
-See the FAULT Pin Configuration Register section for further  +
-details. The SPI CRC feature can be used for both the  +
-transmission and receipt of data packets. +
- +
-==== Reading from Registers ==== +
-The AD5758 has four options for readback mode that can be  +
-configured in the TWO_STAGE_READBACK_SELECT register +
-(see Table 43). These options are as follows: +
- +
-   * Two stage readback mode +
-   * Autostatus readback mode  +
-   * Shared SYNC autostatus readback mode +
-   * Echo mode +
- +
-=== Two Stage Readback Mode === +
-Two stage readback mode consists of a write to the TWO_ +
-STAGE_READBACK_SELECT register to select the register  +
-location to be read back, followed by a NOP command. To  +
-perform a NOP command, write all zeros to Bits[D15:D0] of  +
-the NOP register. During the NOP command, the contents of  +
-the selected register are available on SDO. It is also possible to write a new two stage readback  +
-command during the second frame, such that the corresponding  +
-new data is available on SDO in the subsequent frame. Bits[D31:D30] (or Bits[D23:D22], if SPI CRC is not  +
-enabled) = 0b10 are used as part of the synchronization during  +
-readback. The contents of the first write instruction to the TWO_ +
-STAGE_READBACK_SELECT. +
- +
-=== Autostatus Readback Mode === +
-If autostatus readback mode is selected, the contents of the  +
-status register are available on the SDO line during every SPI  +
-transaction. When reading back the status register, the SDO  +
-contents differ. The autostatus readback mode can be configured via the  +
-READBACK_MODE bits in the two stage readback select  +
-register. +
- +
-=== Shared SYNC Autostatus Readback Mode=== +
-The shared SYNC autostatus readback is a special version of the  +
-autostatus readback mode used to avoid SDO bus contention  +
-when multiple AD5758 devices are sharing the same SYNC line +
-(whereby AD5758 devices are distinguished from each other  +
-using the hardware address pins). After each valid write to a  +
-device, a flag is set. On the subsequent falling edge of SYNC,  +
-the flag is cleared. This mode behaves in a similar manner to  +
-the normal autostatus readback mode, except that the device  +
-does not output the status register contents on SDO when +
-SYNC goes low, unless the internal flag is set (that is, the  +
-previous SPI write was valid). The shared SYNC autostatus readback mode can be  +
-configured via the READBACK_MODE bits in the two stage  +
-readback select register. +
- +
-=== Echo Mode ===  +
-Echo mode behaves in a similar manner to the autostatus  +
-readback mode, except that every second readback consists of  +
-an echo of the previous command written to the AD5758. Echo  +
-mode is useful for checking which SPI instruction was received  +
-in the previous SPI frame. Echo mode can be configured via the  +
-READBACK_MODE bits in the two stage readback select  +
-register. +
- +
-==== SPI Modes ====  +
-SPI has 4 modes that it operates in. CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. CPOL and CPHA bits decide on which edge is the data sampled and shifted. Table 1 below demonstrates SPI modes. +
- +
-{{table_1.png? 328x400}} +
- +
-//Table 1: 4 SPI Modes +
-// +
- +
-==== Writes to AD5758 ==== +
-Figure 1 below shows an example of a flowchart that performs writes to registers.  +
-{{flowchart.png}} +
- +
-//Figure 1: Example Flowchart +
-// +
- +
-=== Reset === +
-Before writing to registers, AD5758 must be reset either by hardware or software. Figure 2 below shows SPI code when AD5758 resets. The top signal is clock frequency. The clock performs 32 oscillations when the green signal /SYNC goes low. Yellow signal is SDI signal. The SPI protocol performs writes to the SDI. From MSB to LSB, the first 3 bits is AD5758 address. Next 5 bits are register address. Next 16 bits is the data sent to the register address that configures that register. Last 8 bits are CRC code. +
- +
-The reset function is in register address 0x08. This is a key register that performs reset by writing 0x15FA to the key register.  +
-{{reset.png?}} +
- +
-//Figure 2: Reset Writes  +
-// +
-=== Clear RESET_OCCURED Bit === +
-Once reset has occurred, RESET_OCCURED bit needs to be cleared that is the 13th bit in DIGITAL_DIAG_RESULTS. Figure 3 below demonstrates 0x2000 written to register 0x14 to clear RESET_OCCURED bit.+
  
-{{rst_occ.png?}}+ 
  
-//Figure 3: RESET_OCCURED Bit Being Cleared +===Writing to a Register===
-//+
  
-=== CLKOUT Configuration === +As shown in the SPI Write Frame table, every SPI write frame contains a slip bit, two address bits, a register address, data and if enabled the CRC will be appended to the SPI frame creating a 32 bit frame. The slip bit must equal the inverse of the MSB − 1 for the frame to be considered valid. The address bits must match the hardware address pins (AD0 and AD1) for the device to accept the SPI frame on the bus. The register address is the address of the register the data will be written to. 
-Default settings are left on 0x09 register. Figure 4 below shows 0x0204 written to GP_CONFIG1 register. +
  
-{{clkout_config.png}}+===SPI Write Frame=== 
 +^  D31      ^  D30:D29       ^   D28:D24             ^  D23:D8   ^  D7:D0  ^ 
 +|  Slip Bit    |  Address Bits    |  Register Address        |  Data  |  CRC  |
  
-//Figure 4: Default GP_CONFIG1 Register Settings +With CRC enabled (default state), the input shift register is 32 bits wide. Data is loaded into the device MSB first, under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If CRC is disabled, the serial interface is reduced to 24 bits; a 32-bit frame is still accepted but the last 8 bits are ignored. \\ 
-//+
  
-=== DC to DC Conversion Settings === +===Reading a Register=== 
-Default settings are left on 0x0c register. Figure 5 below shows 0x0100 written to DCDC_CONFIG2 register.+The default mode for reading back a register is called the two stage readback mode. This mode consists of a write to the TWO_ STAGE_READBACK_SELECT register (Address 0x13) to select the register location to be read back, followed by a NOP command. To perform a NOP command, write all zeros to Bits[D15:D0] of the NOP register (Address 0x00). See the product datasheet for other readback modes. 
  
-{{dcdc.png}}+===SPI Read Frame=== 
 +^  D31:30      ^  D29       ^   D28:D24             ^  D23:D8   ^  D7:D0  ^ 
 +|  10    |  Fault Pin Status    |  Register Address        |  Data  |  CRC  |
  
-//Figure 5: Default DCDC_CONFIG2 Register Settings 
-// 
  
-DC to DC conversion mode is left default. Figure 6 below shows 0x0000 written to DCDC_CONFIG1 register. +=== Performing a Software Reset === 
 +Before initially configuring the device, it is good practice to perform either a hardware or software reset. A software reset is performed by writing 2 keys (0x15FA and 0xAF51) respectively to the key (address 0x08) register. The hardware address pins (AD0 and AD1) are assumed to be logic low for all the following SPI transactions.
  
-{{dcdc2.png}} +Figures 1 and 2 show the first and second software reset key writes. The first write of 0x8815FAA4 can be decoded as
  
-//Figure 6: Default DCDC_CONFIG1 Register Settings +^  D31      ^  D30:D29       ^   D28:D24             ^  D23:D8   ^  D7:D0  ^ 
-//+|  Slip Bit    |  Address Bits    |  Register Address        |  Data  |  CRC  | 
 +|  1  |  00  |   0x08 (01000)  |  0x15FA  |   0xA4  |
  
-=== Disabled DAC Output === +For the second write the data has changed to 0xFA51 and the CRC changed to 0x31.
-DAC output is disabled on default in DAC_CONFIG register. This is shown in figure 7 below.+
  
-{{dac_out_dis.png}} 
  
-//Figure 7: DAC Output Disabled +The oscilloscope plots below show each of the 4 SPI wire data:\\  
-//+<fc #ff00ff>**SCLK**</fc> --> SPI clock\\  
 +<fc #008000>**SYNC**</fc> --> SYNC signal (must be taken low to initiate SPI transfer)\\  
 +<fc #f0e68c>**SDI**</fc> --> Serial Data In (Top line of S1 serial bus)\\  
 +<fc #6495ed>**SDO**</fc> --> Serial Data Out (Bottom line of S1 serial bus)\\  
 +**In the following examples the software driver is configured for SPI mode 1 and the CRC is enabled.**\\ \\ 
  
-Since DAC output is disabled, 0x0000 is written to DAC_INPUT register as shown in figure 8 below.+{{ :resources:eval:user-guides:1st_rst_key.png?nolink&700 |}} 
 +<WRAP centeralign> 
 +//Figure 1 Software Reset Key1 Write 0x8815FAA4// 
 +</WRAP>
  
-{{dac_input.png}}+{{ :resources:eval:user-guides:2nd_rst_key.png?nolink&700 |}} 
 +<WRAP centeralign> 
 +//Figure 2 Software Reset Key2 Write 0x88AF5131// 
 +</WRAP>
  
-//Figure 8: 0x0000 is written to 0x01 register +Figure 3 shows a readback of the default state of the digital diagnostic results register (Address 0x14) before the calibration memory has been refreshed. There are 2 SPI frames visible in the scope plot. Figures 4 and 5 show the first and second SPI frames respectively. The first being the readback command to read the digital diagnostic results register (Address 0x14) and the second shows the NOP command along with the readback data on SDO. The readback data 0x94A0001A on SDO can be decoded as Bits 31:30 = 10,  Fault pin status = 0. Register Address = 0x14, Data = 0xA000 (CAL_MEM_UNREFRESHED = 1 and RESET_OCCURED = 1), CRC = 0x1A
-// +
  
-Writing 0x1DAC to 0x07 register performs a software LDAC update on the device matching the ADDRESS bits within the SPI frame. If  +{{ :resources:eval:user-guides:spi_2_stg_rd.png?nolink&700 |}} 
-the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the AD0 and AD1 bits are ignored and all devices sharing the same SPI  +<WRAP centeralign> 
-bus are updated via the SW_LDAC command. Bits[15:0] of this register always read back as 0x0000. This is shown in figure 9 below.+//Figure 3 Two Stage Readback command// 
 +</WRAP>
  
-{{1dac.png}} 
  
-//Figure 9: 0x1dac is written to SW_LDAC register to switch on LDAC software update +{{ :resources:eval:user-guides:dig_read.png?nolink&700 |}} 
-//+<WRAP centeralign> 
 +//Figure 4 Two Stage Readback command - first frame write 0x93001478// 
 +</WRAP> 
 +{{ :resources:eval:user-guides:rst_sdo_read.png?nolink&700 |}} 
 +<WRAP centeralign> 
 +//Figure 5 Two Stage Readback command - second frame write 0x8000000B (including SDO data 0x94A0001A)// 
 +</WRAP>
  
-DAC output is enabled by writing 0x0c40 to 0x06 register address. 
  
-{{dac_out_en.png}}+=== Calibration Memory Refresh === 
 +After performing a software or hardware reset the next write **must** be a calibration memory refresh. The refresh is performed by writing the key 0xFCBA to the key register (address 0x08). The calibration memory refresh SPI write is 0x88FCBA9D.
  
-//Figure 10: DAC output enabled in DAC_CONFIG register +===Disabling CRC=== 
-//+After performing a calibration refresh the CRC can be disabled if desired. The command to disable the CRC is  Figure 4 shows the SPI write to clear the reset occurred bit. The SPI write to disable the CRC is 0x50005CB7.
  
-To test and see if DAC output is enabled, 0xaaaa is written to DAC_INPUT register. 0xaaaa code should appear on SDI signal on the oscilloscope. This is shown in figure 11 below.+===Clearing Reset Occurred=== 
 +After performing a calibration refresh the device can now be configured as required. The reset occurred bit (Bit 13) in the digital diagnostic results register (Address 0x14) is a logic high and should be cleared. To clear the bit a "1" must be written to clear the bit to a logic 0. The SPI write to clear the reset occurred bit is 0x942000AC. 
  
-{{dac_input_aaaa.png}} 
  
-//Figure 11: 0xaaaa is written to DAC_INPUT register to test and see if DAC output is enabled 
-// 
  
  
 + 
  
  
resources/eval/user-guides/spi.1652171678.txt.gz · Last modified: 10 May 2022 10:34 by Erlandas Petkevicius

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