This version is outdated by a newer approved version.
This version (09 May 2022 18:43) is a draft.
Approvals: 0/1
This version (09 May 2022 18:43) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
Serial Peripheral Interface on AD5758
Slip Bit
A further enhancement to the robustness of the interface is the addition of the slip bit. The MSB of the SPI frame must equal the inverse of the MSB − 1 for the frame to be considered valid. If an incorrect slip bit is detected, the data is ignored and the SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register is asserted.
AD5758 Address Bits
The AD5758 address pins (AD0 and AD1) are used in conjunction with the address bits within the SPI frame to determine which AD5758 device is being addressed by the system controller. With the two address pins, up to four devices can be independently addressed on one board.
SPI Cyclic Redundancy Check
To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8. The device controlling the AD5758 generates an 8-bit frame check sequence using the following polynomial: C(x) = x8 + x2 + x1 + 1 This sequence is added to the end of the data-word, and 32 bits are sent to the AD5758 before taking SYNC high.
If the SPI_CRC_EN bit is set high (default state), the user must supply a frame of exactly 32 bits wide that contains the 24 data bits and 8-bit CRC. If the CRC check is valid, the data is written to the selected register. If the CRC check fails, the data is ignored, the FAULT pin goes low and the FAULT pin status bit and the digital diagnostic status bit (DIG_DIAG_STATUS) in the status register are asserted. A subsequent readback of the DIGITAL_DIAG_RESULTS register reveals that the SPI_CRC_ERR bit is also set. This register is a per bit, write to clear register (see the Sticky Diagnostic Results Bits section); therefore, the SPI_CRC_ERR bit can be cleared by writing a 1 to Bit D0 of the DIGITAL_DIAG_RESULTS register. Doing so clears the SPI_CRC_ERROR bit and causes the FAULT pin to return high (assuming that there are no other active faults). When configuring the FAULT_PIN_CONFIG register, the user can decide whether the SPI CRC error affects the FAULT pin. See the FAULT Pin Configuration Register section for further details. The SPI CRC feature can be used for both the transmission and receipt of data packets.
Reading from Registers
The AD5758 has four options for readback mode that can be configured in the TWO_STAGE_READBACK_SELECT register (see Table 43). These options are as follows: • Two stage readback • Autostatus readback • Shared SYNC autostatus readback • Echo mode
SPI Modes
SPI has 4 modes that it operates in. CPOL bit sets the clocks polarity during the idle state. The CPHA bit selects the clock phase. For mode 0 and mode 1, the idle clock state is low. For mode 2 and mode 3, the idle clock state is high. CPOL and CPHA bits decide on which edge is the data sampled and shifted. Table 1 below demonstrates SPI modes.
Table 1: 4 SPI Modes
Writes to AD5758
Figure 1 below shows an example of a flowchart that performs writes to registers.
Figure 1: Example Flowchart
Reset
Before writing to registers, AD5758 must be reset either by hardware or software. Figure 2 below shows SPI code when AD5758 resets. The top signal is clock frequency. The clock performs 32 oscillations when the green signal /SYNC goes low. Yellow signal is SDI signal. The SPI protocol performs writes to the SDI. From MSB to LSB, the first 3 bits is AD5758 address. Next 5 bits are register address. Next 16 bits is the data sent to the register address that configures that register. Last 8 bits are CRC code.
The reset function is in register address 0x08. This is a key register that performs reset by writing 0x15FA to the key register.
Figure 2: Reset Writes
Clear RESET_OCCURED Bit
Once reset has occurred, RESET_OCCURED bit needs to be cleared that is the 13th bit in DIGITAL_DIAG_RESULTS. Figure 3 below demonstrates 0x2000 written to register 0x14 to clear RESET_OCCURED bit.
Figure 3: RESET_OCCURED Bit Being Cleared
CLKOUT Configuration
Default settings are left on 0x09 register. Figure 4 below shows 0x0204 written to GP_CONFIG1 register.
Figure 4: Default GP_CONFIG1 Register Settings
DC to DC Conversion Settings
Default settings are left on 0x0c register. Figure 5 below shows 0x0100 written to DCDC_CONFIG2 register.
Figure 5: Default DCDC_CONFIG2 Register Settings
DC to DC conversion mode is left default. Figure 6 below shows 0x0000 written to DCDC_CONFIG1 register.
Figure 6: Default DCDC_CONFIG1 Register Settings
Disabled DAC Output
DAC output is disabled on default in DAC_CONFIG register. This is shown in figure 7 below.
Figure 7: DAC Output Disabled
Since DAC output is disabled, 0x0000 is written to DAC_INPUT register as shown in figure 8 below.
Figure 8: 0x0000 is written to 0x01 register
Writing 0x1DAC to 0x07 register performs a software LDAC update on the device matching the ADDRESS bits within the SPI frame. If the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the AD0 and AD1 bits are ignored and all devices sharing the same SPI bus are updated via the SW_LDAC command. Bits[15:0] of this register always read back as 0x0000. This is shown in figure 9 below.
Figure 9: 0x1dac is written to SW_LDAC register to switch on LDAC software update
DAC output is enabled by writing 0x0c40 to 0x06 register address.
Figure 10: DAC output enabled in DAC_CONFIG register
To test and see if DAC output is enabled, 0xaaaa is written to DAC_INPUT register. 0xaaaa code should appear on SDI signal on the oscilloscope. This is shown in figure 11 below.
Figure 11: 0xaaaa is written to DAC_INPUT register to test and see if DAC output is enabled
resources/eval/user-guides/spi.1652114625.txt.gz · Last modified: 09 May 2022 18:43 by Erlandas Petkevicius